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AJvYcCXw9ncec8p4PMLWVi/Uzc1vpJDyLyAKrrrjvnvuYvEC1suoxzczkZsD9Kd7OUutzWZEVIZccKzVAXWE+sQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz0HAh78eRG7qKHRP81Q3YeWMg/GZzQr3eG4l7hZYlA0RSuCyvv PI8VDIbEbBmoLdDRHsAzXZ9FtOc3t/cI9m5LIuYBz+qFox06zUdIQVIOSK0hXaY= X-Google-Smtp-Source: AGHT+IF7jLyp1F9r1R7paqLXL7lZm4mJSG2e31oTisk0Sxja0KjHZpxs+MoHEKQXr+fL0PGmbZlONQ== X-Received: by 2002:a5d:5e0b:0:b0:37c:d244:bdb1 with SMTP id ffacd0b85a97d-37d11311be4mr7478306f8f.26.1728391078001; Tue, 08 Oct 2024 05:37:58 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:41f2:4244:ce34:c273]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43050578facsm20299775e9.19.2024.10.08.05.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 05:37:57 -0700 (PDT) From: Jerome Brunet To: neil.armstrong@linaro.org Cc: George Stark , u.kleine-koenig@pengutronix.de, khilman@baylibre.com, martin.blumenstingl@googlemail.com, linux-pwm@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@salutedevices.com Subject: Re: [PATCH 3/3] pwm: meson: Enable constant and polarity features for g12, axg, s4 In-Reply-To: <5c3a6fdb-e4f0-4a22-9a8d-84baee12769c@linaro.org> (neil armstrong's message of "Tue, 8 Oct 2024 09:31:09 +0200") References: <20241007193203.1753326-1-gnstark@salutedevices.com> <20241007193203.1753326-4-gnstark@salutedevices.com> <5c3a6fdb-e4f0-4a22-9a8d-84baee12769c@linaro.org> Date: Tue, 08 Oct 2024 14:37:56 +0200 Message-ID: <1ja5fesrbv.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue 08 Oct 2024 at 09:31, neil.armstrong@linaro.org wrote: > On 07/10/2024 21:32, George Stark wrote: >> g12, axg and s4 SoC families support constant and polarity bits so enable >> those features in corresponding chip data structs. >> Signed-off-by: George Stark >> --- >> drivers/pwm/pwm-meson.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c >> index 6701738c55e3..c6f032bdfe78 100644 >> --- a/drivers/pwm/pwm-meson.c >> +++ b/drivers/pwm/pwm-meson.c >> @@ -571,26 +571,36 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { >> static const struct meson_pwm_data pwm_axg_ee_data = { >> .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, >> .channels_init = meson_pwm_init_channels_meson8b_legacy, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct meson_pwm_data pwm_axg_ao_data = { >> .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, >> .channels_init = meson_pwm_init_channels_meson8b_legacy, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct meson_pwm_data pwm_g12a_ee_data = { >> .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" }, >> .channels_init = meson_pwm_init_channels_meson8b_legacy, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct meson_pwm_data pwm_g12a_ao_ab_data = { >> .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, >> .channels_init = meson_pwm_init_channels_meson8b_legacy, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct meson_pwm_data pwm_g12a_ao_cd_data = { >> .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL }, >> .channels_init = meson_pwm_init_channels_meson8b_legacy, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct meson_pwm_data pwm_meson8_v2_data = { This needs to be splitted and adjusted as well then. g12 and axg are covered by pwm_meson8_v2_data. >> @@ -599,6 +609,8 @@ static const struct meson_pwm_data pwm_meson8_v2_data = { >> static const struct meson_pwm_data pwm_s4_data = { >> .channels_init = meson_pwm_init_channels_s4, >> + .has_constant = true, >> + .has_polarity = true, >> }; >> static const struct of_device_id meson_pwm_matches[] = { > > Reviewed-by: Neil Armstrong -- Jerome