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Mon, 25 Aug 2025 01:36:25 -0700 (PDT) From: Jerome Brunet To: Da Xue Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Jian Hu , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clk: meson-g12a: fix bit range for fixed sys and hifi pll In-Reply-To: <20250822002203.1979235-1-da@libre.computer> (Da Xue's message of "Thu, 21 Aug 2025 20:22:02 -0400") References: <20250822002203.1979235-1-da@libre.computer> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Mon, 25 Aug 2025 10:36:25 +0200 Message-ID: <1jcy8j6bna.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu 21 Aug 2025 at 20:22, Da Xue wrote: > The bit range 17:0 does not match the datasheet for A311D / S905D3. > Change the bit range to 18:0 for FIX and HIFI PLLs to match datasheet. > > The frac field is missing for sys pll so add that as well. > > Patched: > > + sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \ > /sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq > 996999 > 500000 > + sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary > + grep -i '\(sys_\|hifi_\|fixed_\)pll' > hifi_pll 0 +/-1562Hz > sys_pll_div16 0 +/-1562Hz > sys_pll_cpub_div16 0 +/-1562Hz > + sudo cat /sys/kernel/debug/clk/clk_summary > + grep -i '\(sys_\|hifi_\|fixed_\)pll' > hifi_pll_dco 0 0 0 0 > hifi_pll 0 0 0 0 > sys_pll_dco 1 1 0 3999999985 > sys_pll 0 0 0 499999999 > sys_pll_div16_en 0 0 0 499999999 > sys_pll_div16 0 0 0 31249999 > fixed_pll_dco 1 1 1 3987999985 > fixed_pll 3 3 1 1993999993 > > Unpatch: > > + sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \ > /sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq > 1000000 > 500000 > + sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary > + grep -i '\(sys_\|hifi_\|fixed_\)pll' > hifi_pll 0 +/-1562Hz > sys_pll_div16 0 +/-1562Hz > sys_pll_cpub_div16 0 +/-1562Hz > + sudo cat /sys/kernel/debug/clk/clk_summary > + grep -i '\(sys_\|hifi_\|fixed_\)pll' > hifi_pll_dco 0 0 0 0 > hifi_pll 0 0 0 0 > sys_pll_dco 1 1 0 4800000000 > sys_pll 0 0 0 1200000000 > sys_pll_div16_en 0 0 0 1200000000 > sys_pll_div16 0 0 0 75000000 > fixed_pll_dco 1 1 1 3999999939 > fixed_pll 3 3 1 1999999970 > > Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") > Signed-off-by: Da Xue > --- > drivers/clk/meson/g12a.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index 66f0e817e416..f78cca619ca5 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -157,7 +157,7 @@ static struct clk_regmap g12a_fixed_pll_dco = { > .frac = { > .reg_off = HHI_FIX_PLL_CNTL1, > .shift = 0, > - .width = 17, > + .width = 19, > }, > .l = { > .reg_off = HHI_FIX_PLL_CNTL0, > @@ -223,6 +223,11 @@ static struct clk_regmap g12a_sys_pll_dco = { > .shift = 10, > .width = 5, > }, > + .frac = { > + .reg_off = HHI_SYS_PLL_CNTL1, > + .shift = 0, > + .width = 19, > + }, > .l = { > .reg_off = HHI_SYS_PLL_CNTL0, > .shift = 31, > @@ -1901,7 +1906,7 @@ static struct clk_regmap g12a_hifi_pll_dco = { > .frac = { > .reg_off = HHI_HIFI_PLL_CNTL1, > .shift = 0, > - .width = 17, > + .width = 19, > }, > .l = { > .reg_off = HHI_HIFI_PLL_CNTL0, Thanks for this. While this is indeed the same topic, this is doing 2 things at once. Could you please split this, fixup in one change, adding the missing frac in another ? It is much easier to handle in case something needs to be reverted. -- Jerome