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AJvYcCWgJNgJK34Cxz4/cngzpfNuw3aB62F7vbqLfv+dM5LYql07wwabi129fpcSvezjo6xEMvUXSJUP561yT5M=@vger.kernel.org X-Gm-Message-State: AOJu0YxUet0TBdqqfdSUO708xlp54I/QFIqjfCxh1hTWKBseCbrLxeOv Kjt1aInPt62FZnZLRC1LrYRq/bwrRQ56QlKIo+S5PSQiBjQT1jvyNsysuZU73co= X-Google-Smtp-Source: AGHT+IEkd7fCxmipKdK/jhPqqpXWWRduRKJdf1Fys48euGtYO2BQbNuoCcaPoeGNZkFLXLCk4YE8xA== X-Received: by 2002:a5d:5847:0:b0:37d:4d3f:51e9 with SMTP id ffacd0b85a97d-381c7aa451dmr10370065f8f.40.1730731147068; Mon, 04 Nov 2024 06:39:07 -0800 (PST) Received: from localhost ([2a01:e0a:3c5:5fb1:4393:a9f:472d:9404]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c116abf3sm13387483f8f.101.2024.11.04.06.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 06:39:06 -0800 (PST) From: Jerome Brunet To: Guenter Roeck Cc: Jean Delvare , Jonathan Corbet , Patrick Rudolph , Naresh Solanki , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Delphine CC Chiu , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org Subject: Re: [PATCH v3 3/6] hwmon: (pmbus/core) add wp module param In-Reply-To: (Guenter Roeck's message of "Mon, 4 Nov 2024 06:18:27 -0800") References: <20241024-tps25990-v3-0-b6a6e9d4b506@baylibre.com> <20241024-tps25990-v3-3-b6a6e9d4b506@baylibre.com> <47164712-876e-4bb8-a4fa-4b3d91f2554b@roeck-us.net> <1jjzdj5qyy.fsf@starbuckisacylon.baylibre.com> Date: Mon, 04 Nov 2024 15:39:05 +0100 Message-ID: <1jfro783na.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon 04 Nov 2024 at 06:18, Guenter Roeck wrote: > On 11/4/24 00:43, Jerome Brunet wrote: > >>>> +/* >>>> + * PMBus write protect forced mode: >>>> + * PMBus may come up with a variety of write protection configuration. >>>> + * 'pmbus_wp' may be used if a particular write protection is necessary. >>>> + * The ability to actually alter the protection may also depend on the chip >>>> + * so the actual runtime write protection configuration may differ from >>>> + * the requested one. pmbus_core currently support the following value: >>>> + * - 0: write protection removed >>>> + * - 1: write protection fully enabled, including OPERATION and VOUT_COMMAND >>>> + * registers. Chips essentially become read-only with this. >>> >>> Would it be desirable to also suppport the ability to set the output voltage >>> but not limits (PB_WP_VOUT) ? >> I was starting simple, it is doable sure. >> It is not something I will be able to test on actual since does not >> support that. >> Do you want me to add "2: write protection enable execpt for >> VOUT_COMMAND." ? >> > > Please add it. I have a number of PMBus test boards and will be able to test it. > > Thee are three options, though. Per specification: Any preference for the value mapped to each mode ? Using the one from the spec does not seem practical (32768, 16384, 8192). The bit number, maybe (7, 6, 5) ? or just by order strongest locking ? > > 1000 0000 Disable all writes except to the WRITE_PROTECT command 3 > 0100 0000 Disable all writes except to the WRITE_PROTECT, OPERATION and > PAGE commands 2 > 0010 0000 Disable all writes except to the WRITE_PROTECT, OPERATION, > PAGE, ON_OFF_CONFIG and VOUT_COMMAND commands 1 ? > > The driver uses OPERATION and VOUT_COMMAND, so we should have options > to disable them separately. It may be desirable, for example, to be able > to turn on a regulator but not to change the voltages. Also, since > full write protection also disables writes to the page register, > the impact of full write protection on multi-page chips needs to be > documented. Noted. I'll update the documentation. > > Thanks, > Guenter -- Jerome