[PATCH 2/5] dt-bindings: clock: add Amlogic A5 SCMI clock controller support

Xianwei Zhao via B4 Relay
2024-09-14T05:25:32Z

From: Chuan Liu <chuan.liu@amlogic.com>

Add the SCMI clock controller dt-bindings for Amlogic A5 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
new file mode 100644
index 000000000000..d35d1ff6bab3
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A5_SCMI_CLKC_H
+#define __AMLOGIC_A5_SCMI_CLKC_H
+
+#define CLKID_OSC 0
+#define CLKID_SYS_CLK 1
+#define CLKID_AXI_CLK 2
+#define CLKID_CPU_CLK 3
+#define CLKID_DSU_CLK 4
+#define CLKID_GP1_PLL 5
+#define CLKID_FIXED_PLL_DCO 6
+#define CLKID_FIXED_PLL 7
+#define CLKID_ACLKM 8
+#define CLKID_SYS_PLL_DIV16 9
+#define CLKID_CPU_CLK_DIV16 10
+#define CLKID_FCLK_50M_PREDIV 11
+#define CLKID_FCLK_50M_DIV 12
+#define CLKID_FCLK_50M 13
+#define CLKID_FCLK_DIV2_DIV 14
+#define CLKID_FCLK_DIV2 15
+#define CLKID_FCLK_DIV2P5_DIV 16
+#define CLKID_FCLK_DIV2P5 17
+#define CLKID_FCLK_DIV3_DIV 18
+#define CLKID_FCLK_DIV3 19
+#define CLKID_FCLK_DIV4_DIV 20
+#define CLKID_FCLK_DIV4 21
+#define CLKID_FCLK_DIV5_DIV 22
+#define CLKID_FCLK_DIV5 23
+#define CLKID_FCLK_DIV7_DIV 24
+#define CLKID_FCLK_DIV7 25
+
+#endif /* __AMLOGIC_A5_SCMI_CLKC_H */

--
2.37.1