Re: [PATCH 4/5] clk: meson: add support for the A5 SoC PLL clock

Xianwei Zhao
2024-10-12T05:43:26Z

Hi Jerome,
Thanks for your reply.

On 2024/9/30 17:41, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Sun 29 Sep 2024 at 16:17, Xianwei Zhao <xianwei.zhao@amlogic.com> wrote:
>
>> Hi Jerome,
>> Thanks for your reply.
>>
>> On 2024/9/24 22:45, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>> On Sat 14 Sep 2024 at 13:25, Xianwei Zhao via B4 Relay
>>> <devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>>>
>>>> From: Chuan Liu <chuan.liu@amlogic.com>
>>>>
>>>> Add the PLL clock controller driver for the Amlogic A5 SoC family.
>>>>
>>>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>>> ---
>>>> drivers/clk/meson/Kconfig | 14 ++
>>>> drivers/clk/meson/Makefile | 1 +
>>>> drivers/clk/meson/a5-pll.c | 553 +++++++++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 568 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>>> index 78f648c9c97d..2a713276e46c 100644
>>>> --- a/drivers/clk/meson/Kconfig
>>>> +++ b/drivers/clk/meson/Kconfig
>>>> @@ -132,6 +132,20 @@ config COMMON_CLK_A1_PERIPHERALS
>>>> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
>>>> controller to work.
>>>>
>>>> +config COMMON_CLK_A5_PLL
>>>> + tristate "Amlogic A5 PLL clock controller"
>>>> + depends on ARM64
>>>> + default y
>>>> + imply ARM_SCMI_PROTOCOL
>>> don't think this is needed, same as c3
>>>
>>
>> Will delete it in the next version.
>
>
> Ideally, please trim your replies. This avoid the need for me to dig in
> such long patch and find whatever it is that you replied.
>
> That means, remove text that is not necessary to the reply, leaving the
> necessary context for the discussion.
>
> Also, if it is just to say that 'you will do it', a reply is no
> necessary. Just do it, it will be fine. Reply if you have further
> questions, remarks or do not agree.
>
>>
>>>> + imply COMMON_CLK_SCMI
>>>> + select COMMON_CLK_MESON_REGMAP
>>>> + select COMMON_CLK_MESON_PLL
>>>> + select COMMON_CLK_MESON_CLKC_UTILS
>>>> + help
>>>> + Support for the PLL clock controller on Amlogic AV40x device, AKA A5.
>>>> + Say Y if you want the board to work, because PLLs are the parent
>>>> + of most peripherals.
>>>> +
>>>> config COMMON_CLK_C3_PLL
>>>> tristate "Amlogic C3 PLL clock controller"
>>>> depends on ARM64
>>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>>> index bc56a47931c1..fc4b8a723145 100644
>>>> --- a/drivers/clk/meson/Makefile
>>>> +++ b/drivers/clk/meson/Makefile
>>>> @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>>> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>>>> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
>>>> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
>>>> +obj-$(CONFIG_COMMON_CLK_A5_PLL) += a5-pll.o
>>>> obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
>>>> obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
>>>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>>>> diff --git a/drivers/clk/meson/a5-pll.c b/drivers/clk/meson/a5-pll.c
>>>> new file mode 100644
>>>> index 000000000000..d96ed72ef8d4
>>>> --- /dev/null
>>>> +++ b/drivers/clk/meson/a5-pll.c
>>>> @@ -0,0 +1,553 @@
>
> [...]
>
>>>> +static struct clk_regmap gp0_pll = {
>>>> + .data = &(struct clk_regmap_div_data) {
>>>> + .offset = ANACTRL_GP0PLL_CTRL0,
>>>> + .shift = 16,
>>>> + .width = 3,
>>>> + .table = gp0_pll_od_table,
>>>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "gp0_pll",
>>>> + .ops = &clk_regmap_divider_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &gp0_pll_dco.hw
>>>> + },
>>>> + .num_parents = 1,
>>>> + .flags = CLK_SET_RATE_PARENT,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct reg_sequence hifi_init_regs[] = {
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0X08000000 },
>>> What is bit you are flipping in CTRL0 ? it is suspicious
>>>
>>
>> Yes, CTRL0 and CTRL1 are not necessary here and will be removed in the
>> next version.
>
> That does not really answer my question, does it ?
>

Here it is confirmed with the chip design engineer that the bit27 of
CTRL0 is actually useless, and it is meaningless to write 0 or 1.

>>
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 },
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a295c00 },
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a },
>>>> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x54540000 }
>>>> +};
>>>> +
>>>> +static const struct pll_mult_range hifi_pll_mult_range = {
>>>> + .min = 125,
>>>> + .max = 250,
>>>> +};
>>>> +
>>>> +static struct clk_regmap hifi_pll_dco = {
>>>> + .data = &(struct meson_clk_pll_data) {
>>>> + .en = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 28,
>>>> + .width = 1,
>>>> + },
>>>> + .m = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 0,
>>>> + .width = 8,
>>>> + },
>>>> + .frac = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
>>>> + .shift = 0,
>>>> + .width = 17,
>>>> + },
>>>> + .n = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 10,
>>>> + .width = 5,
>>>> + },
>>>> + .l = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 31,
>>>> + .width = 1,
>>>> + },
>>>> + .rst = {
>>>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 29,
>>>> + .width = 1,
>>>> + },
>>>> + .range = &hifi_pll_mult_range,
>>>> + .init_regs = hifi_init_regs,
>>>> + .init_count = ARRAY_SIZE(hifi_init_regs),
>>>> + .frac_max = 100000,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "hifi_pll_dco",
>>>> + .ops = &meson_clk_pll_ops,
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .fw_name = "xtal_24m",
>>>> + },
>>>> + .num_parents = 1,
>>>> + },
>>>> +};
>>>> +
>>>> +/* The maximum frequency divider supports is 16, not 128(2^7) */
>>>> +static const struct clk_div_table hifi_pll_od_table[] = {
>>>> + { 0, 1 },
>>>> + { 1, 2 },
>>>> + { 2, 4 },
>>>> + { 3, 8 },
>>> Why don't you ajust the mask then ? Looks like a POW_OF_2 basic
>>> dividider to me.
>>>
>>
>> The maximum frequency division value above the design document is 8,
>> such as the configuration 4/5/6... The actual frequency division value
>> is still 8, so this table is defined, why there is this restriction in
>> detail I am not clear about.
>>
>> Will add these comment ot describe it.
>
> I'm not asking you to add a comment.
> With your explanation, my comment still stands.
>
>>
>>>> + { /* sentinel */ }
>>>> +};
>>>> +
>>>> +static struct clk_regmap hifi_pll = {
>>>> + .data = &(struct clk_regmap_div_data) {
>>>> + .offset = ANACTRL_HIFIPLL_CTRL0,
>>>> + .shift = 16,
>>>> + .width = 3,
>>>> + .table = hifi_pll_od_table,
>>>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "hifi_pll",
>>>> + .ops = &clk_regmap_divider_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &hifi_pll_dco.hw
>>>> + },
>>>> + .num_parents = 1,
>>>> + .flags = CLK_SET_RATE_PARENT,
>>>> + },
>>>> +};
>>>> +