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AJvYcCXrJIHX+XrpGwRhGuF9Xp1dCDwLfK06OeEBr1dNUeTo6o42iWYuni5PF0Pk1+lQBg2dzHlRIFei71ix8cM=@vger.kernel.org X-Gm-Message-State: AOJu0Yx+nbE5TweSfZToLxmLK6elr44/SrArjJnE1NINW7RJ0BMpv/Ta ebHTcjLF/8uYX/kEXwl8DdQcQxq7sdqMWg85mp21N9AAskiVB/z9TZM6ILrENZI= X-Google-Smtp-Source: AGHT+IH8H5uUNTbFEsKnYUdKRjBzDDZGcrGLT+W24BeFBC1OCMxsf8Ey3WOHr8h+hmPJhmnT5iK/wg== X-Received: by 2002:a05:600c:3b8e:b0:42b:a9d7:93 with SMTP id 5b1f17b1804b1-42bb032c82cmr45411815e9.28.1725005411476; Fri, 30 Aug 2024 01:10:11 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:90cb:5cec:cfdf:966f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bbd46b60bsm4808145e9.1.2024.08.30.01.10.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 01:10:10 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong Cc: xianwei.zhao@amlogic.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chuan Liu , Kevin Hilman , Martin Blumenstingl , Krzysztof Kozlowski , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 1/3] dt-bindings: clock: fix C3 PLL input parameter In-Reply-To: <0e74dbc8-88ed-43db-95ef-0fe55d92091d@linaro.org> (Neil Armstrong's message of "Fri, 30 Aug 2024 10:00:38 +0200") References: <20240830-c3_add_node-v4-0-b56c0511e9dc@amlogic.com> <20240830-c3_add_node-v4-1-b56c0511e9dc@amlogic.com> <0e74dbc8-88ed-43db-95ef-0fe55d92091d@linaro.org> Date: Fri, 30 Aug 2024 10:10:10 +0200 Message-ID: <1jplpqsa71.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri 30 Aug 2024 at 10:00, Neil Armstrong wrote: > Hi Jerome, > > On 30/08/2024 07:26, Xianwei Zhao via B4 Relay wrote: >> From: Xianwei Zhao >> Add C3 PLL controller input clock parameters "fix". >> The clock named "fix" was initially implemented in PLL clock controller >> driver. However, some registers required secure zone access, so we moved >> it to the secure zone (BL31) and accessed it through SCMI. Since the PLL >> clock driver needs to use this clock, the "fix" clock is used as an input >> source. We updated the driver but forgot to modify the binding accordingly, >> so we are adding it here. >> It is an ABI break but on a new and immature platform. Noboby could >> really >> use that platform at this stage, so nothing is going to break on anyone >> really. >> Fixes: 0e6be855a96d ("dt-bindings: clock: add Amlogic C3 PLL clock >> controller") >> Reviewed-by: Krzysztof Kozlowski >> Signed-off-by: Xianwei Zhao >> --- >> Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml | 7 +++++-- > > So you mind if I take this one via my arm64-dt tree ? There is no conflicting change in my tree so it's fine, yes. > > Neil > > -- Jerome