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* off topic a bit but i realy need help c++ and kernel
@ 2000-11-08  6:42 david
  2000-11-08  9:52 ` Nvidia GeForce2 kernel driver - kernel 2.4.0 test-10 Anthony Chatman
  0 siblings, 1 reply; 4+ messages in thread
From: david @ 2000-11-08  6:42 UTC (permalink / raw)
  To: Linux Kernel List

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hi i am writing a video kernel driver for linux lexos and have got stuck

this is how NVIDIA do their regs

#define NV_PFIFO_RAMHT                                   0x00002210 /*
RW-4R */
#define NV_PFIFO_RAMHT_BASE_ADDRESS                             8:4 /*
RWIUF */
#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000                0x00000010 /*
RWI-V */
#define NV_PFIFO_RAMHT_SIZE                                   17:16 /*
RWIUF */
#define NV_PFIFO_RAMHT_SIZE_4K                           0x00000000 /*
RWI-V */
#define NV_PFIFO_RAMHT_SIZE_8K                           0x00000001 /*
RW--V */
#define NV_PFIFO_RAMHT_SIZE_16K                          0x00000002 /*
RW--V */
#define NV_PFIFO_RAMHT_SIZE_32K                          0x00000003 /*
RW--V */
#define NV_PFIFO_RAMHT_SEARCH                                 25:24 /*
RWIUF */
#define NV_PFIFO_RAMHT_SEARCH_16                         0x00000000 /*
RWI-V */
#define NV_PFIFO_RAMHT_SEARCH_32                         0x00000001 /*
RW--V */
#define NV_PFIFO_RAMHT_SEARCH_64                         0x00000002 /*
RW--V */
#define NV_PFIFO_RAMHT_SEARCH_128                        0x00000003 /*
RW--V */

this can be used like setreg( NV_PFIFO_RAMHT , htbase << ( 0 ?
NV_PFIFO_RAMHT_BASE_ADDRESS)) ;
but i wont to make it better so i tried it this way

#define NV_PFIFO_RAMHT_BASE_ADDRESS 0x00002210:8:4:3 /* address : high
bit : low bit : mode 3 = rw
this seemed much better all on one line so you can do
setreg(NV_PFIFO_RAMHT_BASE_ADDRESS , htbase) ;
but ( 2 ? 1:2:3 ) dose not work
and NV_PFIFO_RAMHT_BASE_ADDRESS 0x00002210,8,4,3 dose not work as
setreg(a,h,l,m) thinks this is
all one agr
the other would be to have it as a big struct

but then compiler can not optimize it ( i think )
if i can use #define 's the it quicker and setreg can be an inline asm
marco

how would it work if i used 64 bit like this

bits 32 - 63 reg address
bits 24 - 31 high bit
bits 16 - 23 low  bit
bits 0  - 7  mode

#define NV_PFIFO_RAMHT_BASE_ADDRESS  0x0000221008040003

so if i sent this to the setreg(unsigned long long , data) asm macro it
would be in EAX:EDX (64 bit)
can the kernel use (long long) and (unsigned long long)  ( 64 bit ints)

that 64 bit way look good but is it ?
                   ( opps i wold need an extr 32 bits for value but can
have 64:32 i think )

has anyone got any help they can give me on this !please email me thank
you!
as i am stuck
also is there a down loadable book on c++ as i am just learning from
others ppl code and really
need a book to do it right

thank you david rundle <sector2@ihug.co.nz>








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Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2000-11-08  6:42 off topic a bit but i realy need help c++ and kernel david
2000-11-08  9:52 ` Nvidia GeForce2 kernel driver - kernel 2.4.0 test-10 Anthony Chatman
2000-11-09  0:08   ` J . A . Magallon
     [not found]     ` <20001109075436.U17457@miggy.org>
2000-11-09 10:09       ` J . A . Magallon

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