[preview] VIA IDE driver v3.11 with vt82c686b UDMA100 support

[preview] VIA IDE driver v3.11 with vt82c686b UDMA100 support

[Vojtech Pavlik]

[-- Attachment #1: Type: text/plain, Size: 309 bytes --]

Hi!

For all of you who had problems getting the VIA IDE driver to work
correctly on the 686b, here is a driver that should work with those
chips, even in UDMA 100 mode. I've not tested it, because I don't have
the 686b myself. So it may eat your filesystem as well.

Good luck!

-- 
Vojtech Pavlik
SuSE Labs

[-- Attachment #2: ide-timing.h --]
[-- Type: text/plain, Size: 8435 bytes --]

#ifndef _IDE_TIMING_H
#define _IDE_TIMING_H

/*
 * $Id: ide-timing.h,v 1.4 2000/10/02 20:48:56 vojtech Exp $
 *
 *  Copyright (c) 1999-2000 Vojtech Pavlik
 *
 *  Sponsored by SuSE
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * Should you need to contact me, the author, you can do so either by
 * e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
 * Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
 */

#include <linux/hdreg.h>

#ifndef XFER_PIO_5
#define XFER_PIO_5		0x0d
#endif

struct ide_timing {
	short mode;
	short setup;	/* t1 */
	short act8b;	/* t2 for 8-bit io */
	short rec8b;	/* t2i for 8-bit io */
	short cyc8b;	/* t0 for 8-bit io */
	short active;	/* t2 or tD */
	short recover;	/* t2i or tK */
	short cycle;	/* t0 */
	short udma;	/* t2CYCTYP/2 */
};

/*
 * PIO 0-5, MWDMA 0-2 and UDMA 0-5 timings (in nanoseconds).
 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
 * for PIO 5, which is a nonstandard extension.
 */

static struct ide_timing ide_timing[] = {

	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0,   0,  20 },
	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0,   0,  30 },
	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0,   0,  45 },

	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0,   0,  60 },
	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0,   0,  80 },
	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0,   0, 120 },
                                          
	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 120,   0 },
	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 150,   0 },
	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 480,   0 },
                                          
	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 240,   0 },
	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 480,   0 },
	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 960,   0 },

	{ XFER_PIO_5,     20,  50,  30, 100,  50,  30, 100,   0 },
	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 120,   0 },
	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 180,   0 },

	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 240,   0 },
	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 383,   0 },
	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 600,   0 },

	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960,   0 },

	{ -1 }
};

#define IDE_TIMING_SETUP	0x01
#define IDE_TIMING_ACT8B	0x02
#define IDE_TIMING_REC8B	0x04
#define IDE_TIMING_CYC8B	0x08
#define IDE_TIMING_8BIT		0x0e
#define IDE_TIMING_ACTIVE	0x10
#define IDE_TIMING_RECOVER	0x20
#define IDE_TIMING_CYCLE	0x40
#define IDE_TIMING_UDMA		0x80
#define IDE_TIMING_ALL		0xff

#define MIN(a,b)	((a)<(b)?(a):(b))
#define MAX(a,b)	((a)>(b)?(a):(b))
#define FIT(v,min,max)	MAX(MIN(v,max),min)
#define ENOUGH(v,unit)	(((v)-1)/(unit)+1)
#define EZ(v,unit)	((v)?ENOUGH(v,unit):0)

#define XFER_MODE	0xf0
#define XFER_UDMA_100	0x44
#define XFER_UDMA_66	0x42
#define XFER_UDMA	0x40
#define XFER_MWDMA	0x20
#define XFER_SWDMA	0x10
#define XFER_EPIO	0x01
#define XFER_PIO	0x00

static short ide_find_best_mode(ide_drive_t *drive, int map)
{
	struct hd_driveid *id = drive->id;
	short best = 0;

	if (!id)
		return XFER_PIO_SLOW;

	if ((map & XFER_UDMA) && (id->field_valid & 4)) {	/* Want UDMA and UDMA bitmap valid */

		if ((map & XFER_UDMA_100) == XFER_UDMA_100)
			if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;

		if ((map & XFER_UDMA_66) == XFER_UDMA_66)
			if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
                	    	    (id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;

                if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
                	    (id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
                	    (id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
	}

	if ((map & XFER_MWDMA) && (id->field_valid & 2)) {	/* Want MWDMA and drive has EIDE fields */

		if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
                	    (id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
                	    (id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0)) return best;
	}

	if (map & XFER_SWDMA) {					/* Want SWDMA */

 		if (id->field_valid & 2) {			/* EIDE SWDMA */

			if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
      				    (id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
				    (id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0)) return best;
		}

		if (id->capability & 1) {			/* Pre-EIDE style SWDMA */

			if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
				    (id->tDMA == 1) ? XFER_SW_DMA_1 :
				    (id->tDMA == 0) ? XFER_SW_DMA_0 : 0)) return best;
		}
	}


	if ((map & XFER_EPIO) && (id->field_valid & 2)) {	/* EIDE PIO modes */

		if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
			    (drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
			    (drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0)) return best;
	}
	
	return  (drive->id->tPIO == 2) ? XFER_PIO_2 :
		(drive->id->tPIO == 1) ? XFER_PIO_1 :
		(drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
}

static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
{
	q->setup   = EZ(t->setup,   T);
	q->act8b   = EZ(t->act8b,   T);
	q->rec8b   = EZ(t->rec8b,   T);
	q->cyc8b   = EZ(t->cyc8b,   T);
	q->active  = EZ(t->active,  T);
	q->recover = EZ(t->recover, T);
	q->cycle   = EZ(t->cycle,   T);
	q->udma    = EZ(t->udma,   UT);
}

static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
{
	if (what & IDE_TIMING_SETUP  ) m->setup   = MAX(a->setup,   b->setup);
	if (what & IDE_TIMING_ACT8B  ) m->act8b   = MAX(a->act8b,   b->act8b);
	if (what & IDE_TIMING_REC8B  ) m->rec8b   = MAX(a->rec8b,   b->rec8b);
	if (what & IDE_TIMING_CYC8B  ) m->cyc8b   = MAX(a->cyc8b,   b->cyc8b);
	if (what & IDE_TIMING_ACTIVE ) m->active  = MAX(a->active,  b->active);
	if (what & IDE_TIMING_RECOVER) m->recover = MAX(a->recover, b->recover);
	if (what & IDE_TIMING_CYCLE  ) m->cycle   = MAX(a->cycle,   b->cycle);
	if (what & IDE_TIMING_UDMA   ) m->udma    = MAX(a->udma,    b->udma);
}

static struct ide_timing* ide_timing_find_mode(short speed)
{
	struct ide_timing *t;

	for (t = ide_timing; t->mode != speed; t++)
		if (t->mode < 0)
			return NULL;
	return t; 
}

static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
{
	struct hd_driveid *id = drive->id;
	struct ide_timing *s, p;

/*
 * Find the mode.
 */

	if (!(s = ide_timing_find_mode(speed)))
		return -EINVAL;

/*
 * If the drive is an EIDE drive, it can tell us it needs extended
 * PIO/MWDMA cycle timing.
 */

	if (id && id->field_valid & 2) {	/* EIDE drive */

		memset(&p, 0, sizeof(p));

		switch (speed & XFER_MODE) {

			case XFER_PIO:
				if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
						    else p.cycle = p.cyc8b = id->eide_pio_iordy;
				break;

			case XFER_MWDMA:
				p.cycle = id->eide_dma_min;
				break;
		}

		ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
	}

/*
 * Convert the timing to bus clock counts.
 */

	ide_timing_quantize(s, t, T, UT);

/*
 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
 * and some other commands. We have to ensure that the DMA cycle timing is
 * slower/equal than the fastest PIO timing.
 */

	if ((speed & XFER_MODE) != XFER_PIO) {
		ide_timing_compute(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
		ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
	}

/*
 * Lenghten active & recovery time so that cycle time is correct.
 */

	if (t->act8b + t->rec8b < t->cyc8b) {
		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
		t->rec8b = t->cyc8b - t->act8b;
	}

	if (t->active + t->recover < t->cycle) {
		t->active += (t->cycle - (t->active + t->recover)) / 2;
		t->recover = t->cycle - t->active;
	}

	return 0;
}

#endif

[-- Attachment #3: via82cxxx.c --]
[-- Type: text/plain, Size: 16337 bytes --]

/*
 * $Id: via82cxxx.c,v 3.11 2001/01/10 12:33:60 vojtech Exp $
 *
 *  Copyright (c) 2000 Vojtech Pavlik
 *
 *  Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 *  Sponsored by SuSE
 */

/*
 * VIA IDE driver for Linux. Supports
 *
 *   vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233
 *
 * southbridges, which can be found in
 *
 *  VIA Apollo VP, VPX, VPX/97, VP2, VP2/97, VP3, MVP3, MVP4, P6, Pro,
 *  Pro Plus, Pro 133, Pro 133A, ProMedia PM601, ProSavage PM133, PLE133,
 *  Pro 266, KX133, KT133, ProSavage KM133, KT133A, KT266
 *  PC-Chips VXPro, VXPro+, TXPro-III, TXPro-AGP, ViaGra, BXToo, BXTel
 *  AMD 640, 640 AGP, 750 IronGate
 *  ETEQ 6618, 6628, 6638
 *  Micron Samurai
 *
 * chipsets. Supports
 *
 *   PIO 0-5, MWDMA 0-2, SWDMA 0-2 and UDMA 0-5
 *
 * (this includes UDMA33, 66 and 100) modes. UDMA66 and higher modes are
 * autodetected only in case the BIOS has detected a 80 wire cable. To ignore
 * the BIOS data, use 'ide0=ata66' or 'ide1=ata66' on the kernel command line.
 * You may also need to configure the kernel IDE driver to ignore byte93 UDMA66
 * enable bits if your drives don't use them correctly to achieve UDMA66/100
 * operation.
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * Should you need to contact me, the author, you can do so either by
 * e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
 * Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#include "ide-timing.h"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_UDMA		0x07
#define VIA_UDMA_NONE		0x00
#define VIA_UDMA_33		0x01
#define VIA_UDMA_66		0x02
#define VIA_UDMA_100		0x03
#define VIA_FIFO_SIZE		0x08
#define VIA_THR0_3041		0x10
#define VIA_THR0_RMI		0x20
#define VIA_CMDTIME		0x40

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	unsigned short id;
	unsigned char rev;
	unsigned char flags;
} via_isa_bridges[] = {
	{ "vt8233",		PCI_DEVICE_ID_VIA_8233_0,   0x00, VIA_UDMA_100 },
	{ "vt8231",		PCI_DEVICE_ID_VIA_8231,     0x00, VIA_UDMA_66 },
	{ "vt82c686b",		PCI_DEVICE_ID_VIA_82C686,   0x40, VIA_UDMA_100 | VIA_FIFO_SIZE },
	{ "vt82c686a (cf/cg)",	PCI_DEVICE_ID_VIA_82C686,   0x20, VIA_UDMA_66 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c686a (cd/ce)",	PCI_DEVICE_ID_VIA_82C686,   0x10, VIA_UDMA_66 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c686",		PCI_DEVICE_ID_VIA_82C686,   0x00, VIA_UDMA_66 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c596b (cf/cg)",	PCI_DEVICE_ID_VIA_82C596,   0x20, VIA_UDMA_66 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c596b (cd/ce)",	PCI_DEVICE_ID_VIA_82C596,   0x10, VIA_UDMA_66 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c596a",		PCI_DEVICE_ID_VIA_82C596,   0x00, VIA_UDMA_33 | VIA_CMDTIME | VIA_THR0_RMI },
	{ "vt82c586b (3041)",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, VIA_UDMA_33 | VIA_CMDTIME | VIA_FIFO_SIZE | VIA_THR0_3041},
	{ "vt82c586b (3040)",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, VIA_UDMA_33 | VIA_CMDTIME | VIA_FIFO_SIZE },
	{ "vt82c586a",		PCI_DEVICE_ID_VIA_82C586_0, 0x20, VIA_UDMA_33 | VIA_CMDTIME | VIA_FIFO_SIZE },
	{ "vt82c586",		PCI_DEVICE_ID_VIA_82C586_0, 0x00, VIA_UDMA_NONE | VIA_CMDTIME },
	{ NULL }
};

static struct via_isa_bridge *via_config;
static unsigned char via_enabled;
static unsigned int via_80w;

/*
 * VIA /proc entry.
 */

#ifdef CONFIG_PROC_FS

#include <linux/stat.h>
#include <linux/proc_fs.h>

int via_proc, via_base;
static struct pci_dev *bmide_dev, *isa_dev;
extern int (*via_display_info)(char *, char **, off_t, int); /* ide-proc.c */

static char *via_control3[] = { "No limit", "64", "128", "192" };

#define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define via_print_drive(name, format, arg...)\
	p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");

static int via_get_info(char *buffer, char **addr, off_t offset, int count)
{
	short pci_clock, speed[4], cycle[4], setup[4], active[4],
		recover[4], uen[4], udma[4], active8b[4], recover8b[4];
	struct pci_dev *dev = bmide_dev;
	unsigned int v, u, i;
	unsigned short c, w;
	unsigned char t, x;
	char *p = buffer;

	via_print("----------VIA BusMastering IDE Configuration----------------");

	via_print("Driver Version:                     3.11");
	via_print("South Bridge:                       VIA %s", via_config->name);

	pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
	pci_read_config_byte(dev, PCI_REVISION_ID, &x);
	via_print("Revision:                           ISA %#x IDE %#x", t, x);

	via_print("BM-DMA base:                        %#x", via_base);
	via_print("PCI clock:                          %dMHz", pci_clock = system_bus_clock());

	pci_read_config_byte(dev, VIA_MISC_1, &t);
	via_print("Master Read  Cycle IRDY:            %dws", (t & 64) >> 6);
	via_print("Master Write Cycle IRDY:            %dws", (t & 32) >> 5);
	via_print("BM IDE Status Register Read Retry:  %s", (t & 8) ? "yes" : "no");

	pci_read_config_byte(dev, VIA_MISC_3, &t);
	via_print("Max DRDY Pulse Width:               %s%s", via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : "");

	via_print("-----------------------Primary IDE-------Secondary IDE------");
	via_print("Read DMA FIFO flush:   %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no");
	via_print("End Sector FIFO flush: %10s%20s", (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no");

	pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
	via_print("Prefetch Buffer:       %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
	via_print("Post Write Buffer:     %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &t);
	via_print("Enabled:               %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");

	c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8);
	via_print("Simplex only:          %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");

	via_print("Cable Type:            %10s%20s", (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w");

	via_print("-------------------drive0----drive1----drive2----drive3-----");

	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
	pci_read_config_word(dev, VIA_8BIT_TIMING, &w);

	if (via_config->flags & VIA_UDMA)
		pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	else u = 0;

	for (i = 0; i < 4; i++) {
		setup[i]     = ((t >> ((3 - i) << 1)) & 0x3) + 1;
		recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
		active8b[i]  = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
		active[i]    = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
		recover[i]   = ((v >> ((3 - i) << 3)) & 0xf) + 1;

		udma[i] = (((u >> ((3 - i) << 3)) & 0x7) + 2) *
			(((via_config->flags & VIA_UDMA) == VIA_UDMA_100) ? 2 : (((u >> (((3 - i) & 2) << 3)) & 0x8) ? 3 : 6));
		uen[i]  = ((u >> ((3 - i) << 3)) & 0x20) ? 1 : 0;

		speed[i] = 120 * pci_clock / (uen[i] ? udma[i] : (active[i] + recover[i]) * 6);
		cycle[i] = 1000 / pci_clock * (uen[i] ? udma[i] : (active[i] + recover[i]) * 6) / 6;
	}

	via_print_drive("Transfer Mode: ", "%10s",
			(c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2)) ? (uen[i] ? "UDMA" : "DMA") : "PIO");

	via_print_drive("Address Setup: ", "%8dns", (1000 / pci_clock) * setup[i]);
	via_print_drive("Cmd Active:    ", "%8dns", (1000 / pci_clock) * active8b[i]);
	via_print_drive("Cmd Recovery:  ", "%8dns", (1000 / pci_clock) * recover8b[i]);
	via_print_drive("Data Active:   ", "%8dns", (1000 / pci_clock) * active[i]);
	via_print_drive("Data Recovery: ", "%8dns", (1000 / pci_clock) * recover[i]);
	via_print_drive("Cycle Time:    ", "%8dns", cycle[i]);
	via_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 10, speed[i] % 10);

	return p - buffer;	/* hoping it is less than 4K... */
}

#endif

/*
 * via_set_speed() writes timing values to the chipset registers
 */

static void via_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
{
	unsigned char t;

	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);

	if (via_config->flags & VIA_CMDTIME)
		pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
			((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch(via_config->flags & VIA_UDMA) {
		case VIA_UDMA_33:  t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
		case VIA_UDMA_66:  t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
		case VIA_UDMA_100: t = timing->udma ? (0xf0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
		default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/*
 * via_set_drive() computes timing values configures the drive and
 * the chipset to a desired transfer mode. It also can be called
 * by upper layers.
 */

static int via_set_drive(ide_drive_t *drive, unsigned char speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct ide_timing t, p;
	int err, T, UT;

	if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
		if ((err = ide_config_drive_speed(drive, speed)))
			return err;

	T = 1000 / system_bus_clock();
	UT = T / MAX(via_config->flags & VIA_UDMA, 1);

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);

	if (!drive->init_speed)	
		drive->init_speed = speed;
	drive->current_speed = speed;

	return 0;
}

/*
 * via82cxxx_tune_drive() is a callback from upper layers for
 * PIO-only tuning.
 */

static void via82cxxx_tune_drive(ide_drive_t *drive, unsigned char pio)
{
	if (!((via_enabled >> HWIF(drive)->channel) & 1))
		return;

	if (pio == 255) {
		via_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
		return;
	}

	via_set_drive(drive, XFER_PIO_0 + MIN(pio, 5));
}

#ifdef CONFIG_BLK_DEV_IDEDMA

/*
 * via82cxxx_dmaproc() is a callback from upper layers that can do
 * a lot, but we use it for DMA/PIO tuning only, delegating everything
 * else to the default ide_dmaproc().
 */

int via82cxxx_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
{

	if (func == ide_dma_check) {

		short w80 = eighty_ninty_three(drive);

		short speed = ide_find_best_mode(drive,
			XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
			(via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
			(w80 && (via_config->flags & VIA_UDMA) == VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
			(w80 && (via_config->flags & VIA_UDMA) == VIA_UDMA_100 ? XFER_UDMA_100 : 0));

		func = ((speed & XFER_MODE) != XFER_PIO) ? ide_dma_on : ide_dma_off_quietly;

		if (via_set_drive(drive, speed))
			func = ide_dma_off;
	}

	return ide_dmaproc(func, drive);
}

#endif /* CONFIG_BLK_DEV_IDEDMA */

/*
 * The initialization callback. Here we determine the IDE chip type
 * and initialize its drive independent registers.
 */

unsigned int __init pci_init_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	unsigned char t, v;
	unsigned int u;
	int i;

/*
 * Find ISA bridge to see how good the IDE is.
 */

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((isa = pci_find_device(PCI_VENDOR_ID_VIA, via_config->id, NULL))) {
			pci_read_config_byte(isa, PCI_REVISION_ID, &t);
			if (t >= via_config->rev)
				break;
		}

	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, contact Vojtech Pavlik <vojtech@suse.cz>\n");
		return -ENODEV;
	}

/*
 * Check 80-wire cable presence.
 */

	switch (via_config->flags & VIA_UDMA) {

		case VIA_UDMA_100:

			pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
			for (i = 24; i >= 0; i -= 8)
				if ((u >> i) & 0x10)					/* BIOS 80-wire bit enabled */
					via_80w |= (1 << (1 - (i >> 4)));
			break;

		case VIA_UDMA_66:
		
			pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
			pci_write_config_dword(dev, VIA_UDMA_TIMING, u | 0x80008);
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) && (((u >> i) & 7) < 2))	/* 2x PCI clock && less than 3T/cycle */
					via_80w |= (1 << (1 - (i >> 4)));
			break;
	}

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	via_enabled = ((v & 1) ? 2 : 0) | ((v & 2) ? 1 : 0);

/*
 * Set up FIFO sizes and thresholds.
 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	if (via_config->flags & VIA_FIFO_SIZE) {

		t =  (t & 0x90) | 0x0a;					/* 50% FIFO threshold */
		switch (via_enabled) {
			case 1: t |= 0x00; break;			/* all on primary */
			case 2: t |= 0x60; break;			/* all on secondary */
			case 3: t |= 0x20; break;			/* fifo evenly distributed */
		}

	} else t = (t & 0xf0) | 0x0a;

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

/*
 * Set up the rest of FIFO stuff.
 */

	pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
	pci_write_config_byte(dev, VIA_IDE_CONFIG, t | 0xf0);		/* prefetch & postwrite */

	if (via_config->flags & VIA_THR0_3041) {
		pci_read_config_byte(dev, VIA_MISC_1, &t);		/* 0% FIFO threshold */
		pci_write_config_byte(dev, VIA_MISC_1, t | 0x03);
	}

	if (via_config->flags & VIA_THR0_RMI) {
		pci_read_config_byte(dev, VIA_MISC_2, &t);		/* 0% FIFO threshold, fast memory */
		pci_write_config_byte(dev, VIA_MISC_2, (t & 0xf0) | 0x03);
	}

	pci_read_config_byte(dev, VIA_MISC_3, &t);
	pci_write_config_byte(dev, VIA_MISC_3, t | 0xf0);		/* enable FIFO flushing */

/*
 * Print the boot message.
 */

	printk(KERN_INFO "VP_IDE: VIA %s IDE %s controller on pci%d:%d.%d\n",
			via_config->name,
			(via_config->flags & VIA_UDMA) == VIA_UDMA_100 ? "UDMA100" :
			(via_config->flags & VIA_UDMA) == VIA_UDMA_66 ? "UDMA66" :
			(via_config->flags & VIA_UDMA) == VIA_UDMA_33 ? "UDMA33" : "MWDMA16",
			dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
/*
 * Register /proc/ide/via entry
 */

#ifdef CONFIG_PROC_FS
	if (!via_proc) {
		for (i = 0; i < 6; i++)
                	if (pci_resource_flags(dev, i) & IORESOURCE_IO)
                        	break;
		
		via_base = pci_resource_start(dev, i);
		bmide_dev = dev;
		isa_dev = isa;
		via_display_info = &via_get_info;
		via_proc = 1;

	}
#endif

	return 0;
}

unsigned int __init ata66_via82cxxx(ide_hwif_t *hwif)
{
	return ((via_enabled & via_80w) >> hwif->channel) & 1;
}

void __init ide_init_via82cxxx(ide_hwif_t *hwif)
{
	int i;

	hwif->tuneproc = &via82cxxx_tune_drive;
	hwif->speedproc = &via_set_drive;
	hwif->autodma = 0;

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

#ifdef CONFIG_BLK_DEV_IDEDMA
	if (hwif->dma_base) {
		hwif->dmaproc = &via82cxxx_dmaproc;
		hwif->autodma = 1;
	}
#endif /* CONFIG_BLK_DEV_IDEDMA */
}

/*
 * We allow the BM-DMA driver only work on enabled interfaces.
 */

void __init ide_dmacapable_via82cxxx(ide_hwif_t *hwif, unsigned long dmabase)
{
	if ((via_enabled >> hwif->channel) & 1)
		ide_setup_dma(hwif, dmabase, 8);
}

Re: [preview] VIA IDE driver v3.11 with vt82c686b UDMA100 support

[John O'Donnell]

Vojtech Pavlik wrote:

> Hi!
> 
> For all of you who had problems getting the VIA IDE driver to work
> correctly on the 686b, here is a driver that should work with those
> chips, even in UDMA 100 mode. I've not tested it, because I don't have
> the 686b myself. So it may eat your filesystem as well.
> 
> Good luck!

Oops - I did not look close enough.  I have the 686a.
Well, it works the same  :-)

ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
VP_IDE: IDE controller on PCI bus 00 dev 21
VP_IDE: chipset revision 16
VP_IDE: not 100% native mode: will probe irqs later
VP_IDE: VIA vt82c686a (cf/cg) IDE UDMA66 controller on pci0:4.1
     ide0: BM-DMA at 0xb800-0xb807, BIOS settings: hda:DMA, hdb:pio
     ide1: BM-DMA at 0xb808-0xb80f, BIOS settings: hdc:DMA, hdd:DMA
hda: WDC WD450AA-00BAA0, ATA DISK drive
hdc: Hewlett-Packard CD-Writer Plus 9100, ATAPI CDROM drive
hdd: LS-120 VER5 00 UHD Floppy, ATAPI FLOPPY drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
ide1 at 0x170-0x177,0x376 on irq 15
hda: 87930864 sectors (45021 MB) w/2048KiB Cache, CHS=5473/255/63, UDMA(33)
hdd: 123264kB, 963/8/32 CHS, 533 kBps, 512 sector size, 720 rpm

Timing tests are the same....

-- 
<SomeLamer> what's the difference between chattr and chmod?
<SomeGuru> SomeLamer: man chattr > 1; man chmod > 2; diff -u 1 2 | less
	-- Seen on #linux on irc
=== Never ask a geek why, just nod your head and slowly back away.===
+==============================+====================================+
| John O'Donnell (Sr. Systems Engineer, Net Admin, Webmaster, etc.) |
| Voice FX Corporation (a subsidiary of Student Advantage)          |
| One Plymouth Meeting         |     E-Mail: johnod@voicefx.com     |
| Suite 610                    |           www.voicefx.com          |
| Plymouth Meeting, PA 19462   |         www.campusdirect.com       |
+==============================+====================================+

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RE:[preview] VIA IDE driver v3.11 with vt82c686b UDMA100 support

[Chandler, Alan]

On Wed Jan 10 2001 - 06:45:24 EST Vojtech Pavlik <vojtech@suse.cz> wrote

>For all of you who had problems getting the VIA IDE driver to work 
>correctly on the 686b, here is a driver that should work with those 
>chips, even in UDMA 100 mode. I've not tested it, because I don't have 
>the 686b myself. So it may eat your filesystem as well. 

Although not subscribed to the list (so please cc any comments to me at 
alan@chandlerfamily.org.uk) , I have been tracking the various comments
with errors on VIA IDE drivers under 2.4.0 as I have been experiencing them
myself.

I have been reading the code in vt82cxxx.c in the ide directory of the linux
source
to try and understand what was happening. One thing in the code has been
bugging me as
not right, and although the code attatched to the above message from Vojtech
seems to
sidestep the problem the underlying issue seems still to be there.
[Apologies I am
on a business trip to the US so I cannot access it directly]

within the original code in 2.4.0 there is a table of timings for the
various transfer modes
(I assume they are in 10**-9 secs) - lets call any particular value t.

There is then a piece of code that creates T = 1000/pci_bus_speed which I
assume is the time
of a bus-cycle in 10**-9 secs.

There seems a calculation t/T to calculate the number of bus clocks needed
to meet the
timings above which will get loaded into the ide controller.  There appears
to be a
macro called ENOUGH to do this and I am assuming it is called "ENOUGH"
because it tries to
be a little generous so that the timing is not tight.

The calculation this macro does is (t-1)/(T+1) - AND THIS IS THE CRUX OF MY
POINT but this
seems to me to give a number TOO SMALL, not too large (as desired).

I would like to change this (maybe to (t+1)/(T-1) to see if it fixes the
problem but 

a) I am not at home with access to a machine, and
b) If I am totally mistaken about this I might hose my disks

It seemed more appropriate to seek the indulgence of this list to get
another opinions
as to whether I have misunderstood what the code is trying to do before
taking this step.

I can be reached on chandlera@logica.com until approx 4:00pm EST 17th Jan or
alan@chandlerfamily.org.uk from Sat afternoon (UK time).




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Re: [preview] VIA IDE driver v3.11 with vt82c686b UDMA100 support

[Vojtech Pavlik]

Hi!

The macro is defined as (in your symbols):

(((t)-1)/(T)+1)

The same macro is used both in 2.1e (2.4.0 driver) and in 3.11
(686b-capable driver). If you minimize the parentheses, you'll get:

E = (t-1)/T + 1

Which gives the correct answer. We need E*T >= t.

Vojtech

On Wed, Jan 17, 2001 at 02:38:00PM -0000, Chandler, Alan wrote:
> On Wed Jan 10 2001 - 06:45:24 EST Vojtech Pavlik <vojtech@suse.cz> wrote
> 
> >For all of you who had problems getting the VIA IDE driver to work 
> >correctly on the 686b, here is a driver that should work with those 
> >chips, even in UDMA 100 mode. I've not tested it, because I don't have 
> >the 686b myself. So it may eat your filesystem as well. 
> 
> Although not subscribed to the list (so please cc any comments to me at 
> alan@chandlerfamily.org.uk) , I have been tracking the various comments
> with errors on VIA IDE drivers under 2.4.0 as I have been experiencing them
> myself.
> 
> I have been reading the code in vt82cxxx.c in the ide directory of the linux
> source
> to try and understand what was happening. One thing in the code has been
> bugging me as
> not right, and although the code attatched to the above message from Vojtech
> seems to
> sidestep the problem the underlying issue seems still to be there.
> [Apologies I am
> on a business trip to the US so I cannot access it directly]
> 
> within the original code in 2.4.0 there is a table of timings for the
> various transfer modes
> (I assume they are in 10**-9 secs) - lets call any particular value t.
> 
> There is then a piece of code that creates T = 1000/pci_bus_speed which I
> assume is the time
> of a bus-cycle in 10**-9 secs.
> 
> There seems a calculation t/T to calculate the number of bus clocks needed
> to meet the
> timings above which will get loaded into the ide controller.  There appears
> to be a
> macro called ENOUGH to do this and I am assuming it is called "ENOUGH"
> because it tries to
> be a little generous so that the timing is not tight.
> 
> The calculation this macro does is (t-1)/(T+1) - AND THIS IS THE CRUX OF MY
> POINT but this
> seems to me to give a number TOO SMALL, not too large (as desired).
> 
> I would like to change this (maybe to (t+1)/(T-1) to see if it fixes the
> problem but 
> 
> a) I am not at home with access to a machine, and
> b) If I am totally mistaken about this I might hose my disks
> 
> It seemed more appropriate to seek the indulgence of this list to get
> another opinions
> as to whether I have misunderstood what the code is trying to do before
> taking this step.
> 
> I can be reached on chandlera@logica.com until approx 4:00pm EST 17th Jan or
> alan@chandlerfamily.org.uk from Sat afternoon (UK time).
> 
> 
> 
> 
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> Please read the FAQ at http://www.tux.org/lkml/

-- 
Vojtech Pavlik
SuSE Labs
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