From: "J . A . Magallon" <jamagallon@able.es>
To: Linux Kernel <linux-kernel@vger.kernel.org>
Subject: APIC asymmetry in SMP ?
Date: Tue, 1 May 2001 16:39:47 +0200 [thread overview]
Message-ID: <20010501163947.A1278@werewolf.able.es> (raw)
Hi,
Looking over one other problem, I realized that my 2 cpus are recognized
slightly different in the <setup_APIC_timer> function:
cpu: 0, clocks: 1002324, slice: 334108
CPU0<T0:1002320,T1:668208,D:4,S:334108,C:1002324>
cpu: 1, clocks: 1002324, slice: 334108
CPU1<T0:1002320,T1:334096,D:8,S:334108,C:1002324>
Both are just the same, both pII@400, 512Kb:
CPU: Before vendor init, caps: 0183fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 512K
Intel machine check reporting enabled on CPU#0.
CPU: After vendor init, caps: 0183fbff 00000000 00000000 00000000
CPU: After generic, caps: 0183fbff 00000000 00000000 00000000
CPU: Common caps: 0183fbff 00000000 00000000 00000000
CPU0: Intel Pentium II (Deschutes) stepping 02
.
CPU: Before vendor init, caps: 0183fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 512K
CPU: After vendor init, caps: 0183fbff 00000000 00000000 00000000
CPU: After generic, caps: 0183fbff 00000000 00000000 00000000
CPU: Common caps: 0183fbff 00000000 00000000 00000000
CPU1: Intel Pentium II (Deschutes) stepping 02
???
--
J.A. Magallon # Let the source
mailto:jamagallon@able.es # be with you, Luke...
Linux werewolf 2.4.4-ac1 #1 SMP Tue May 1 11:35:17 CEST 2001 i686
reply other threads:[~2001-05-01 14:41 UTC|newest]
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