Re: VIA's Southbridge bug: Latest (pseudo-)patch

[Marc Lehmann <pcg@goof.com>]

On Sat, May 19, 2001 at 11:07:21AM +0200, Axel Thimm <Axel.Thimm@physik.fu-berlin.de> wrote:
> if( KT133A || KT133 || KX133 ) {
>   if( Mainboard=="Epox 8KTA-3(+)" && BIOS>="8kt31417" )
>     return 0; /* EPOX already fixed it their way. */
> #ifdef NEW_PATCH
>   Offset 76: Set bit5=0 and bit4=1 ("every PCI master grand")
> #else /* this is already part of 2.4.4 */
>   Offset 70: Set bit1=0 ("PCI Delay Transaction = 0")

one thing I found out using triel and error is that setting "PCI Delay
Transaction" to enabled causes data corruption on WRITE to my ide drives
connected to an Promise Ultra 100 PCI controlelr (I didn't get any
corruption on the devices connected to the via ide interface, presumably
because my bios already had the right fix).

So, while the every pci master grant setting apperently fixes the internal
via ide interface corruption the PCI Delay Transaction option also must be
buggy (or my promise controller is) and causes data corruption at least
with an additional promise ultra 100.

board: asus cuv4x-d (Apollo MVP3 AGP + via686b southbridge)

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