From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Tue, 3 Jul 2001 20:20:31 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Tue, 3 Jul 2001 20:20:22 -0400 Received: from mail1.bigmailbox.com ([209.132.220.32]:9997 "EHLO mail1.bigmailbox.com") by vger.kernel.org with ESMTP id ; Tue, 3 Jul 2001 20:20:01 -0400 Date: Tue, 3 Jul 2001 17:19:55 -0700 Message-Id: <200107040019.RAA26151@mail1.bigmailbox.com> Content-Type: text/plain Content-Disposition: inline Content-Transfer-Encoding: binary X-Mailer: MIME-tools 4.104 (Entity 4.116) Mime-Version: 1.0 X-Originating-Ip: [64.40.39.165] From: "Colin Bayer" To: linux-kernel@vger.kernel.org Cc: rddunlap@osdlab.org Subject: Re: Sticky IO-APIC problem Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org "Randy.Dunlap" wrote: >What mobo (model/name) is it? >Can you give us the output from "lspci -vv"? OK, it's an Intel BN810E Desktop Board; here's the output from lspci -vv: [root@fortytwo /root]# lspci -vv 00:00.0 Host bridge: Intel Corporation 82810E GMCH [Graphics Memory Controller Hub] (rev 03) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- FastB2B- 00:1f.0 ISA bridge: Intel Corporation 82801AA ISA Bridge (LPC) (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- This shows that Linux mapped the APIC (part of the processor). >It says nothing about mapping any IO APICs (unless you deleted >that part :). Oops, sorry -- misunderstood the meaning of the message. 8-P >So, how does one know if a (UP) system has an IO APIC and that >Linux can be configured to use the UP IO APIC code?... > >(That's a serious question: does an IO APIC show up in lspci output?) > >And why do you think that this system has an IO APIC? >Is it documented to have one? >[just digging for clues] There's no IO-APIC in the lspci output, but that's because it's integrated as part of the i810 chipset; it's probably hidden to keep people from tinkering with the settings -- there's not much one can do to modify an interrupt controller that wouldn't end badly 8=;-) (according to Intel's docs, the IO-APIC's carried somewhere on the 82801AA I/O Controller Hub, and I quote:) >>From Intel's 82801AA I/O Controller Hub Datasheet (http://developer.intel.com/design/chipsets/datashts/29065503.pdf): Features List: (page 3) ... - Interrupt Controller - Two cascaded 82C59 - Integrated IO-APIC capability - 15 Interrupt support in 8259 mode, 24 Interrupt support in IO-APIC mode ... 82801AA Simplified Block Diagram: (page 4) ____________ SERIRQ <-----------> | | PIRQ[A..D]# <------> | | IRQ[14..15] -------> | Interrupt |<--- APICCLK -----------> | | APICD[1..0] <------> |___________| 82801AA Datasheet Introduction: (page 25) Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible interrupt controller (PIC) described in the previous section, the ICH incorporates the Advanced Programmable Interrupt Controller (APIC). While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multi-processor system. Hope this clears up some confusion. -- Colin ------------------------------------------------------------ The CompNerd Network: http://www.compnerd.com/ Where a nerd can be a nerd. Get your free webmail@compnerd.net!