Question about using the kernel dma_cache_...() defines in asm/io.h

[James Bottomley <James.Bottomley@HansenPartnership.com>]

I'm currently writing a SCSI device driver that can be used on multiple 
platforms, some of which don't preserve DMA cache coherency like the x86 does.

I know the basics of how to use the dma_cache_wback(), dma_cache_inv() and 
dma_cache_wback_inv() functions, however the question has come up about what I 
should do in the edge cases where the memory I want the device to write to 
shares a cache line with some other kernel data that I don't control.  Since 
some CPU chip architectures only support cache control bits per cache line 
rather than per byte, if I invalidate my range of data I could potentially 
cause the destruction of cached but unflushed data sharing the cache line.

I suspect that it is the intention of these cache coherency functions to 
operate without regard for neighbouring data, and that this could be enforced 
on architectures like the above by restricting the minimum kernel memory 
allocation alignment to be the cache line width.

Could the designer of these functions step forward and confirm how they are 
supposed to be used?

Thanks,

James Bottomley