booting SMP P6 kernel on P4 hangs.

booting SMP P6 kernel on P4 hangs.

[Tigran Aivazian]

Hi guys,

Isn't SMP P6 kernel supposed to boot fine on a P4? Btw, booting with
"nosmp" works but booting with "noapic" hangs just the same.

Here is where it hangs:

> 
> ---------------------System Info------------------------------------
> 
> Intel Pentium 4 processor: 1.3 GHz
> Level 2 Cache: 256 KB Integrated
> 
> System Memory 256 MB ECC RDRAM
> AGP Aperture  128 MB
> CPU Information::
>   CPU speed   Normal
>   Bus Speed  100 Mhz
>   Processor ID F0A
>   Clock Speed 1.30 Ghz
>   Cache Size  256KB
> 
> 
> 
> --------------------Messages on the screen---------------------------
> 
> 
> CPU0: Intel(R) Pentium(R) 4 CPU 1300 Mhz stepping 0a
> per-CPU timeslice cutoff: 731.49 usecs
> weird, boot CPU (#0) not listed by the BIOS
> Getting VERSION: f000acde
> Getting VERSION: f0ffac21
> leaving PIC mode, enabling symmetric IO mode.
> enabled ExtINT on CPU#0
> ESR value before enabling vector: 00000000
> ESR value after enabling vector: 00000000
> CPU present map: 1
> Before bogomips.
> Error: only one processor found.
> Boot done.
> ENABLING IO-APIC IRQs
> Synchronizing Arb IDs.
> ..TIMER: vector=31 pin1=2 pin2=0
> activating NMI Watchdog...done
> CPU#0 NMI appears to be stuck
> testing the IO APIC.............
> ..........................done
> calibrating APIC timer...
> .....CPU clock speed is 1285.2614 Mhz
> ....host bus clock speed is 0.0000 Mhz
> cpu:0, clocks:0, slice:0
> 
> 
> 

Re: booting SMP P6 kernel on P4 hangs.

[Linus Torvalds]

In article <Pine.LNX.4.21.0107310705580.1374-100000@penguin.homenet> you write:
>
>Isn't SMP P6 kernel supposed to boot fine on a P4? Btw, booting with
>"nosmp" works but booting with "noapic" hangs just the same.

It should boot, and it looks like the problem may be a bad MP table.

The fact that it gets to the point of saying "only one processor found"
definitely means that it found a MP table.  However, that MP table
doesn't seem to actually describe the (single) CPU in a way that Linux
likes:

>> CPU0: Intel(R) Pentium(R) 4 CPU 1300 Mhz stepping 0a
>> per-CPU timeslice cutoff: 731.49 usecs
>> weird, boot CPU (#0) not listed by the BIOS

Notice? 

It looks like your MP table does list a CPU, but it doesn't match the
CPU that is the boot CPU. So first Linux is unhappy about not finding
the boot CPU, but once it has added it it gets to the point of trying to
use the "other" CPU (the one described in the MP table):

>> CPU#0 NMI appears to be stuck
>> testing the IO APIC.............
>> ..........................done
>> calibrating APIC timer...
>> .....CPU clock speed is 1285.2614 Mhz
>> ....host bus clock speed is 0.0000 Mhz
>> cpu:0, clocks:0, slice:0

And yeah, that's not going anywhere.

The way Linux gets the boot CPU ID is by reading the APIC ID. It's
supposed to match the one in the MP table.

The reason "nosmp" works for you is that then we just ignore the MP
table, and just use the boot CPU without worrying about anything else. 

		Linus

Re: booting SMP P6 kernel on P4 hangs.

[Arjan van de Ven]

Linus Torvalds wrote:
> 
> In article <Pine.LNX.4.21.0107310705580.1374-100000@penguin.homenet> you write:
> >
> >Isn't SMP P6 kernel supposed to boot fine on a P4? Btw, booting with
> >"nosmp" works but booting with "noapic" hangs just the same.
> 
> It should boot, and it looks like the problem may be a bad MP table.

Oh it is. And it's due to a recommendation Intel makes to bios writers. 
As a result, every P4 I've encountered shares this bug. Intel knows it's
an invalid MP table, but refuses to change the recommendation.

Now all Linux installers that decide to install a SMP kernel if they
encounter
a MPTABLE already have a "except if it's a P4" exception nowadays..

Greetings,
   Arjan van de Ven

Re: booting SMP P6 kernel on P4 hangs.

[Tigran Aivazian]

On Wed, 1 Aug 2001, Arjan van de Ven wrote:
> Now all Linux installers that decide to install a SMP kernel if they
> encounter
> a MPTABLE already have a "except if it's a P4" exception nowadays..

that assumes that the installer itself has to be a UP kernel, which means
the installation cannot itself serve as a "demo" of the final product in
the fullest possible capacity... Not good, can't we workaround that
somehow during parsing of the mp table?

Regards,
Tigran

Re: booting SMP P6 kernel on P4 hangs.

[Maciej W. Rozycki]

On Wed, 1 Aug 2001, Arjan van de Ven wrote:

> Oh it is. And it's due to a recommendation Intel makes to bios writers. 
> As a result, every P4 I've encountered shares this bug. Intel knows it's
> an invalid MP table, but refuses to change the recommendation.

 Where's the recommendation?  We might work it around somehow. 

 Alternatively we may just disable the SMP mode if the bootstrap CPU's
real ID contradits the one in the MP table. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

Re: booting SMP P6 kernel on P4 hangs.

[Alan Cox]

> On Wed, 1 Aug 2001, Arjan van de Ven wrote:
> 
> > Oh it is. And it's due to a recommendation Intel makes to bios writers. 
> > As a result, every P4 I've encountered shares this bug. Intel knows it's
> > an invalid MP table, but refuses to change the recommendation.
> 
>  Where's the recommendation?  We might work it around somehow. 
> 
>  Alternatively we may just disable the SMP mode if the bootstrap CPU's
> real ID contradits the one in the MP table. 

I think just disable SMP in that case. There are currently no SMP Pentium IV
boxes and perhaps Intel will have fixed it by the time SMP Pentium IV exists

Re: booting SMP P6 kernel on P4 hangs.

[john slee]

On Thu, Aug 02, 2001 at 01:30:53PM +0100, Alan Cox wrote:
> I think just disable SMP in that case. There are currently no SMP Pentium IV
> boxes and perhaps Intel will have fixed it by the time SMP Pentium IV exists

yes there are, they may not be available to the general public yet
however:

http://anandtech.com/cpu/showdoc.html?i=1472&p=5

j.

-- 
"Bobby, jiggle Grandpa's rat so it looks alive, please" -- gary larson

Re: booting SMP P6 kernel on P4 hangs.

[Alan Cox]

> On Thu, Aug 02, 2001 at 01:30:53PM +0100, Alan Cox wrote:
> > I think just disable SMP in that case. There are currently no SMP Pentium IV
> > boxes and perhaps Intel will have fixed it by the time SMP Pentium IV exists
> 
> yes there are, they may not be available to the general public yet
> however:
> 
> http://anandtech.com/cpu/showdoc.html?i=1472&p=5

Which gives intel plenty of time to fix their bios problems. Right now the
situation is we are seeing Pentium IV boxes reporting invalid MP 1.4 specs
and dying. Reporting an invalid MP spec and booting single user at least 
ensures people can boot their boxes while intel fixes their problems

Re: booting SMP P6 kernel on P4 hangs.

[Chris Wedgwood]

On Thu, Aug 02, 2001 at 03:50:05PM +0100, Alan Cox wrote:

    Which gives intel plenty of time to fix their bios problems. Right
    now the situation is we are seeing Pentium IV boxes reporting
    invalid MP 1.4 specs and dying. Reporting an invalid MP spec and
    booting single user at least ensures people can boot their boxes
    while intel fixes their problems

I assume these things, even with busted MP tables will work under
Win2k as it will use ACPI tables instead (I'm assuming they are
available abd valid?).

What about NT4?  If that can also use ACPI tables (I can't see how, it
predates ACPI I think) then it may well be Linux is the only thing
that stil uses MP tables and hence won't boot in such machines :(



  --cw

Re: booting SMP P6 kernel on P4 hangs.

[Steffen Persvold]

john slee wrote:
> 
> On Thu, Aug 02, 2001 at 01:30:53PM +0100, Alan Cox wrote:
> > I think just disable SMP in that case. There are currently no SMP Pentium IV
> > boxes and perhaps Intel will have fixed it by the time SMP Pentium IV exists
> 
> yes there are, they may not be available to the general public yet
> however:
> 
> http://anandtech.com/cpu/showdoc.html?i=1472&p=5
> 

Hmm, we have two dual Pentium IV systems here in our lab, and they are
available to the public (atleast SuperMicro & Tyan makes them). This is however
Pentium IV Xeon chips (i.e not plain Pentium IV) and they use the Intel 860
chipset. I've not seen any problems yet with these system (using RedHat 7.1
with 2.4.3-12smp kernel).

Regards,
-- 
  Steffen Persvold               Systems Engineer
  Email : mailto:sp@scali.no     Scali AS (http://www.scali.com)
  Tlf   : (+47) 22 62 89 50      Olaf Helsets vei 6
  Fax   : (+47) 22 62 89 51      N-0621 Oslo, Norway

Re: booting SMP P6 kernel on P4 hangs.

[Linus Torvalds]

On Wed, 1 Aug 2001, Arjan van de Ven wrote:
> >
> > It should boot, and it looks like the problem may be a bad MP table.
>
> Oh it is. And it's due to a recommendation Intel makes to bios writers.
> As a result, every P4 I've encountered shares this bug. Intel knows it's
> an invalid MP table, but refuses to change the recommendation.

What's the recommendation? We might be able to change the specific code in
question..

Or are they just trying to strongarm the move to the horrid ACPI tables?

		Linus

Re: booting SMP P6 kernel on P4 hangs.

[Alan Cox]

> On Wed, 1 Aug 2001, Arjan van de Ven wrote:
> > >
> > > It should boot, and it looks like the problem may be a bad MP table.
> >
> > Oh it is. And it's due to a recommendation Intel makes to bios writers.
> > As a result, every P4 I've encountered shares this bug. Intel knows it's
> > an invalid MP table, but refuses to change the recommendation.
> 
> What's the recommendation? We might be able to change the specific code in
> question..
> 
> Or are they just trying to strongarm the move to the horrid ACPI tables?

They are certainly involved in the latter but whether this is related  or 
a seperate evil empire scheme is open to question

Re: booting SMP P6 kernel on P4 hangs.

[Mark Hemment]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 2006 bytes --]

Hi,

On Tue, 31 Jul 2001, Linus Torvalds wrote:
> In article <Pine.LNX.4.21.0107310705580.1374-100000@penguin.homenet> you write:
> >
> >Isn't SMP P6 kernel supposed to boot fine on a P4? Btw, booting with
> >"nosmp" works but booting with "noapic" hangs just the same.
>
> It should boot, and it looks like the problem may be a bad MP table.


  The problem is the MP table contains no configuration blocks, and a zero
local APIC address.  I've attached the full boot messages.

  The work around is trap that there are no config blocks, and fall back
to UP.  Patch attached.

Mark



diff -ur -X dontdiff linux-2.4.7/arch/i386/kernel/apic.c p4-2.4.7/arch/i386/kernel/apic.c
--- linux-2.4.7/arch/i386/kernel/apic.c	Wed Jun 20 18:06:38 2001
+++ p4-2.4.7/arch/i386/kernel/apic.c	Fri Aug  3 11:10:55 2001
@@ -345,9 +345,8 @@
 {
 	unsigned long apic_phys;

-	if (smp_found_config) {
-		apic_phys = mp_lapic_addr;
-	} else {
+	apic_phys = mp_lapic_addr;
+	if (!apic_phys) {
 		/*
 		 * set up a fake all zeroes page to simulate the
 		 * local APIC and another one for the IO-APIC. We
diff -ur -X dontdiff linux-2.4.7/arch/i386/kernel/mpparse.c p4-2.4.7/arch/i386/kernel/mpparse.c
--- linux-2.4.7/arch/i386/kernel/mpparse.c	Tue Jun 12 02:15:27 2001
+++ p4-2.4.7/arch/i386/kernel/mpparse.c	Fri Aug  3 11:04:18 2001
@@ -306,6 +306,23 @@
 	mp_lapic_addr = mpc->mpc_lapic;

 	/*
+	 * Buggy BIOS work around.
+	 * Some BIOSes report an MP table, with correct signature, checksum,
+	 * etc, but with no configuration blocks.
+	 * In this case fall back to UP.
+	 *
+	 * Note: On a system which showed this problem, the local APIC
+	 * address was given as NULL.  This may not be the case for all
+	 * systems, so take the address (incase it is valid) and check it
+	 * init_apic_mappings().
+	 */
+	if (count >= mpc->mpc_length) {
+		printk("Short mptable - assuming UP system\n");
+		smp_found_config = 0;
+		return 1;
+	}
+
+	/*
 	 *	Now process the configuration blocks.
 	 */
 	while (count < mpc->mpc_length) {

[-- Attachment #2: bootmsg --]
[-- Type: TEXT/PLAIN, Size: 4469 bytes --]

Linux version 2.4.7-VxOS (root@einstein) (gcc version egcs-2.91.66
19990314/Lin
x (egcs-1.1.2 release)) #1 SMP Sun Jul 29 17:07:50 BST 2001
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 00000000000a0000 (usable)
 BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000000ff87000 (usable)
 BIOS-e820: 000000000ff87000 - 000000000ffa6000 (ACPI data)
 BIOS-e820: 000000000ffa6000 - 0000000010000000 (reserved)
 BIOS-e820: 00000000fec00000 - 00000000fec10000 (reserved)
 BIOS-e820: 00000000fee00000 - 00000000fee10000 (reserved)
 BIOS-e820: 00000000ffb00000 - 0000000100000000 (reserved)
Scan SMP from 40000000 for 1024 bytes.
Scan SMP from 4009fc00 for 1024 bytes.
Scan SMP from 400f0000 for 65536 bytes.
found SMP MP-table at 000fe710
hm, page 000fe000 reserved twice.
hm, page 000ff000 reserved twice.
hm, page 000f0000 reserved twice.
On node 0 totalpages: 65415
zone(0): 4096 pages.
zone(1): 61319 pages.
zone(2): 0 pages.
Intel MultiProcessor Specification v1.4
    IMCR and PIC compatibility mode.
OEM ID: DELL     Product ID: WS 330       APIC at: 0x0
BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw
vendor)
Bus #0 is ISA
Int: type 0, pol 0, trig 0, bus 0, IRQ 00, APIC ID 0, APIC INT 02
Int: type 0, pol 0, trig 0, bus 0, IRQ 01, APIC ID 0, APIC INT 01
Int: type 0, pol 0, trig 0, bus 0, IRQ 03, APIC ID 0, APIC INT 03
Int: type 0, pol 0, trig 0, bus 0, IRQ 04, APIC ID 0, APIC INT 04
Int: type 0, pol 0, trig 0, bus 0, IRQ 05, APIC ID 0, APIC INT 05
Int: type 0, pol 0, trig 0, bus 0, IRQ 06, APIC ID 0, APIC INT 06
Int: type 0, pol 0, trig 0, bus 0, IRQ 07, APIC ID 0, APIC INT 07
Int: type 0, pol 0, trig 0, bus 0, IRQ 08, APIC ID 0, APIC INT 08
Int: type 0, pol 0, trig 0, bus 0, IRQ 09, APIC ID 0, APIC INT 09
Int: type 0, pol 0, trig 0, bus 0, IRQ 0a, APIC ID 0, APIC INT 0a
Int: type 0, pol 0, trig 0, bus 0, IRQ 0b, APIC ID 0, APIC INT 0b
Int: type 0, pol 0, trig 0, bus 0, IRQ 0c, APIC ID 0, APIC INT 0c
Int: type 0, pol 0, trig 0, bus 0, IRQ 0d, APIC ID 0, APIC INT 0d
Int: type 0, pol 0, trig 0, bus 0, IRQ 0e, APIC ID 0, APIC INT 0e
Int: type 0, pol 0, trig 0, bus 0, IRQ 0f, APIC ID 0, APIC INT 0f
Int: type 3, pol 0, trig 0, bus 0, IRQ 00, APIC ID 0, APIC INT 00
Processors: 0
mapped APIC to ffffe000 (00000000)
Kernel command line: auto BOOT_IMAGE=linux-nopae ro root=305
BOOT_FILE=/boot/vm
inuz-2.4.7-nopae console=ttyS0,9600 console=tty0
Initializing CPU#0
Detected 1285.359 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 2562.45 BogoMIPS
Memory: 253632k/261660k available (1445k kernel code, 7644k reserved, 1139k
dat
, 352k init, 0k highmem)
kdb version 1.8 by Scott Lurndal, Keith Owens. Copyright SGI, All Rights
Reserv
d
Dentry-cache hash table entries: 32768 (order: 6, 262144 bytes)
Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes)
Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
CPU: L1 I cache: 12K, L1 D cache: 8K
CPU: L2 cache: 256K
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch@atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: L1 I cache: 12K, L1 D cache: 8K
CPU: L2 cache: 256K
Intel machine check reporting enabled on CPU#0.
CPU0: Intel(R) Pentium(R) 4 CPU 1300MHz stepping 0a
per-CPU timeslice cutoff: 731.49 usecs.
weird, boot CPU (#0) not listed by the BIOS.
Getting VERSION: f000acde
Getting VERSION: f0ffac21
leaving PIC mode, enabling symmetric IO mode.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
CPU present map: 1
Before bogomips.
Error: only one processor found.
Boot done.
ENABLING IO-APIC IRQs
Synchronizing Arb IDs.
..TIMER: vector=31 pin1=2 pin2=0
activating NMI Watchdog ... done.
CPU#0 NMI appears to be stuck.
testing the IO APIC.......................
.................................... done.
calibrating APIC timer ...
..... CPU clock speed is 1285.3667 MHz.
..... host bus clock speed is 0.0000 MHz.
cpu: 0, clocks: 0, slice: 0

Re: booting SMP P6 kernel on P4 hangs.

[Maciej W. Rozycki]

On Fri, 3 Aug 2001, Mark Hemment wrote:

>   The problem is the MP table contains no configuration blocks, and a zero
> local APIC address.  I've attached the full boot messages.
> 
>   The work around is trap that there are no config blocks, and fall back
> to UP.  Patch attached.

 The following patch should be better -- all the handling is performed at
the table parsing stage as it should.  Could you please test it?  It
applies to -ac7 cleanly as well. 

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

patch-2.4.7-null_apic-4
diff -up --recursive --new-file linux-2.4.7.macro/arch/i386/kernel/mpparse.c linux-2.4.7/arch/i386/kernel/mpparse.c
--- linux-2.4.7.macro/arch/i386/kernel/mpparse.c	Thu Jul  5 12:21:27 2001
+++ linux-2.4.7/arch/i386/kernel/mpparse.c	Mon Aug  6 10:16:54 2001
@@ -273,24 +273,26 @@ static int __init smp_read_mpc(struct mp
 	int count=sizeof(*mpc);
 	unsigned char *mpt=((unsigned char *)mpc)+count;
 
-	if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
-	{
+	if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
 		panic("SMP mptable: bad signature [%c%c%c%c]!\n",
 			mpc->mpc_signature[0],
 			mpc->mpc_signature[1],
 			mpc->mpc_signature[2],
 			mpc->mpc_signature[3]);
-		return 1;
+		return 0;
 	}
-	if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
-	{
+	if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
 		panic("SMP mptable: checksum error!\n");
-		return 1;
+		return 0;
 	}
-	if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04)
-	{
-		printk("Bad Config Table version (%d)!!\n",mpc->mpc_spec);
-		return 1;
+	if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
+		printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
+			mpc->mpc_spec);
+		return 0;
+	}
+	if (!mpc->mpc_lapic) {
+		printk(KERN_ERR "SMP mptable: null local APIC address!\n");
+		return 0;
 	}
 	memcpy(str,mpc->mpc_oem,8);
 	str[8]=0;
@@ -358,6 +360,8 @@ static int __init smp_read_mpc(struct mp
 			}
 		}
 	}
+	if (!num_processors)
+		printk(KERN_ERR "SMP mptable: no processors registered!\n");
 	return num_processors;
 }
 
@@ -508,8 +512,12 @@ void __init get_smp_config (void)
 		 * Read the physical hardware table.  Anything here will
 		 * override the defaults.
 		 */
-		smp_read_mpc((void *)mpf->mpf_physptr);
-
+		if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
+			smp_found_config = 0;
+			printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
+			printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
+			return;
+		}
 		/*
 		 * If there are no explicit MP IRQ entries, then we are
 		 * broken.  We set up most of the low 16 IO-APIC pins to

Re: booting SMP P6 kernel on P4 hangs.

[Mark Hemment]

On Mon, 6 Aug 2001, Maciej W. Rozycki wrote:

> On Fri, 3 Aug 2001, Mark Hemment wrote:
>
> >   The problem is the MP table contains no configuration blocks, and a zero
> > local APIC address.  I've attached the full boot messages.
> >
> >   The work around is trap that there are no config blocks, and fall back
> > to UP.  Patch attached.
>
>  The following patch should be better -- all the handling is performed at
> the table parsing stage as it should.  Could you please test it?  It
> applies to -ac7 cleanly as well.


  I can't test it at the moment (machine in the States - me in the UK),
but looking at the check against a NULL local APIC address it will trap
the case on the reported box.

Mark

Re: booting SMP P6 kernel on P4 hangs.

[Mikael Pettersson]

On Tue, 31 Jul 2001 07:10:34 +0100 (BST), Tigran Aivazian wrote:

>Isn't SMP P6 kernel supposed to boot fine on a P4? Btw, booting with
>"nosmp" works but booting with "noapic" hangs just the same.
>
>Here is where it hangs:
>
>> CPU0: Intel(R) Pentium(R) 4 CPU 1300 Mhz stepping 0a
>> per-CPU timeslice cutoff: 731.49 usecs
>> weird, boot CPU (#0) not listed by the BIOS
>> Getting VERSION: f000acde
>> Getting VERSION: f0ffac21
>> leaving PIC mode, enabling symmetric IO mode.
>> enabled ExtINT on CPU#0
>> ESR value before enabling vector: 00000000
>> ESR value after enabling vector: 00000000
>> CPU present map: 1
>> Before bogomips.
>> Error: only one processor found.
>> Boot done.
>> ENABLING IO-APIC IRQs
>> Synchronizing Arb IDs.
>> ..TIMER: vector=31 pin1=2 pin2=0
>> activating NMI Watchdog...done
>> CPU#0 NMI appears to be stuck
>> testing the IO APIC.............
>> ..........................done
>> calibrating APIC timer...
>> .....CPU clock speed is 1285.2614 Mhz
>> ....host bus clock speed is 0.0000 Mhz
>> cpu:0, clocks:0, slice:0

Which kernel version?
I actually wouldn't expect the current local APIC or SMP code to
work perfectly on a P4, since there are many differences to P6/K7.
I scribbled some of them down a while ago (based on reading
the first rev of Intel's IA32 Vol3 for P4 manual):
- FEE000090 Arbitration Priority not supported in P4
- broadcast is 0xFF in P4
- flat cluster model is not supported in P4
- focus processor concept doesn't exist in P4
- "all excluding self" destination shorthand == "all including self"
  in P4 if lowest-priority delivery mode is used (not recommended)
- SPIV bit 9 (focus) should be 0 on P4
- version is 0x14 and maxlvt is 5 on P4

2.4.7 apic.c enables the SPIV focus bit, maybe that's the problem.

/Mikael

Re: booting SMP P6 kernel on P4 hangs.

[Petr Vandrovec]

On  1 Aug 01 at 10:47, Tigran Aivazian wrote:
> On Wed, 1 Aug 2001, Arjan van de Ven wrote:
> > Now all Linux installers that decide to install a SMP kernel if they
> > encounter
> > a MPTABLE already have a "except if it's a P4" exception nowadays..
> 
> that assumes that the installer itself has to be a UP kernel, which means
> the installation cannot itself serve as a "demo" of the final product in
> the fullest possible capacity... Not good, can't we workaround that
> somehow during parsing of the mp table?

MPTABLE is not what kills us. What kills us is stupid code
in setup_APIC_clocks(), which calls setup_APIC_timer even if 
calibrate_APIC_clock() finds that '...host bus clock speed is 0.0000 MHz'
But setup_APIC_timer does not handle this condition at all
and ends in endless loop waiting for internal APIC timer to decrement.
But for some unknown reason (either Intel braindamage or motherboard
vendor braindamage) most of (all?) P4 have just non-counting timer
in its APIC.

As I do not have P4 here, I do not know whether correct solution
is to disable APIC on P4 at all because of it does not work, or
whether only timer portion of APIC is broken on P4.

UNTESTED change could look like (btw it also fixes APIC aware Linux
kernel not booting in VMware on machine which has APIC):

void __int setup_APIC_clocks (void) {
      __cli();
      calibration_result = calibrate_APIC_clock();
      /*
       * Now set up the timer for real.
       */
      if (calibration_result) {
         using_apic_timer = 1;
         setup_APIC_timer((void*)calibration_result);
         __sti();
         printk("Using local APIC timer interrupts.\n");
         smp_call_function(setup_APIC_timer, (void*)calibration_result, 1, 1);
      } else {
         __sti();
         printk("Local APIC timer unusable.\n");
      }
}

                                            Best regards,
                                                Petr Vandrovec
                                                vandrove@vc.cvut.cz