From: Dave Jones <davej@suse.de>
To: Linus Torvalds <torvalds@transmeta.com>,
Alan Cox <alan@lxorguk.ukuu.org.uk>,
Linux Kernel <linux-kernel@vger.kernel.org>
Subject: [PATCH] Pentium IV cacheline size.
Date: Sat, 13 Oct 2001 12:57:33 +0100 [thread overview]
Message-ID: <20011013125733.A10917@suse.de> (raw)
Currently, we're using a L1_CACHE_SHIFT value of 7
for Pentium 4, which equates to 128 byte cache lines.
Curious, I dumped the info on the only P4 I could find,
and noticed they were 64 byte.
Upon checking the documentation, they're 64 byte there too.
Is this just a thinko on someones part, or was there a
rationale behind this that I've not realised ?
If it is wrong, patch below sets it back to 64 bytes.
regards,
Dave.
diff -urN --exclude-from=/home/davej/.exclude linux/arch/i386/config.in linux-dj/arch/i386/config.in
--- linux/arch/i386/config.in Fri Oct 12 16:29:57 2001
+++ linux-dj/arch/i386/config.in Sat Oct 13 12:40:19 2001
@@ -108,7 +108,7 @@
define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
fi
if [ "$CONFIG_MPENTIUM4" = "y" ]; then
- define_int CONFIG_X86_L1_CACHE_SHIFT 7
+ define_int CONFIG_X86_L1_CACHE_SHIFT 6
define_bool CONFIG_X86_TSC y
define_bool CONFIG_X86_GOOD_APIC y
define_bool CONFIG_X86_PGE y
--
| Dave Jones. http://www.codemonkey.org.uk
| SuSE Labs .
next reply other threads:[~2001-10-13 11:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-10-13 11:57 Dave Jones [this message]
2001-10-13 16:31 ` [PATCH] Pentium IV cacheline size Mark Hahn
2001-10-13 17:34 ` Linus Torvalds
-- strict thread matches above, loose matches on Subject: below --
2001-10-13 14:17 Mikael Pettersson
2001-10-13 14:27 ` Dave Jones
2001-10-13 18:24 Manfred Spraul
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