Re: Athlon PSE/AGP Bug

[Andrea Arcangeli <andrea@suse.de>]

On Tue, Jan 22, 2002 at 12:43:59AM +0000, Russell King wrote:
> On Tue, Jan 22, 2002 at 01:37:43AM +0100, Andrea Arcangeli wrote:
> > On Mon, Jan 21, 2002 at 02:19:31PM -0800, David S. Miller wrote:
> > > That's not true, see the ptrace() helper code.  Russell King pointed
> > > this out to me last week and it's on my TODO list to fix it up.
> > 
> > Where? :) ptrace doesn't change pagetables, no need to flush any tlb in
> > ptrace.
> 
> See:
> 
> int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write)
> {
> ...
>                 flush_cache_page(vma, addr);
> ...
> }
> 
> flush_cache_page() is passed a non-page aligned address.  AFAIK that is
> the only instance where the flush_{cache,tlb}_* stuff is called with
> non-page aligned addresses.

flush_cache_page is by no means a _tlb_ flush. It is a virtual indexed
cache flush needed before you can access data at such address (noop on
x86).

I'm not even sure that we should consider incorrect if anybody would do
a tlb flush on a not aligned address, also given it works fine for the
4k pages, I mainly wanted to point out that with tlb flushes it gets
pretty natural to do them aligned in the code, and that's what linux
does with the 4k pages (we never invalidate 4M pages as Dave pointed out
but it sounds unlikely nvidia tlb flush 4M pages misaligned).

Andrea