Re: readl/writel and memory barriers

[Jesse Barnes <jbarnes@sgi.com>]

On Tue, Feb 19, 2002 at 09:10:44AM -0800, David Mosberger wrote:
> On ia64, the fact that readl()/writel() are accessing uncached space
> ensures the CPU doesn't reorder the accesses.  Furthermore, the
> accesses are performed through "volatile" pointers, which ensures that
> the compiler doesn't reorder them (and, as a side-effect, such
> pointers also generate ordered loads/stores, but this isn't strictly
> needed, due to accessing uncached space).

Making a variable volatile doesn't guarantee that the compiler won't
reorder references to it, AFAIK.  And on some platforms, even uncached
I/O references aren't necessarily ordered.

To avoid the overhead of having I/O flushed on every memory barrier
and readX/writeX operation, we've introduced mmiob() on ia64, which
explicity orders I/O space accesses.  Some ports have chosen to take
the performance hit in every readX/writeX, memory barrier, and
spinlock however (e.g. PPC64, MIPS).

Is this a reasonable approach?  Is it acceptable to have a seperate
barrier operation for I/O space?  If so, perhaps other archs would be
willing to add mmiob() ops?

Thanks,
Jesse