Re: [PATCH] Support for assymmetric SMP

[Andrea Arcangeli <andrea@suse.de>]

On Mon, Mar 11, 2002 at 12:25:49PM +0100, Kurt Garloff wrote:
> Hi Andrea,
> 
> On Mon, Mar 11, 2002 at 05:29:54AM +0100, Andrea Arcangeli wrote:
> > the only problem is if you happen to get the timer irq always in the
> > same cpu for a few seconds, then the last_tsc_low will wrap around and
> > gettimeofday will be wrong. And even if you snapshot the full 64bit of the
> > tsc you'll run into some trouble if the timer irq will be delivered only
> > to the same cpu for a long time (for example if you use irq bindings).
> > you'd lose precision and you'll run into the measuration errors of
> > fast_gettimeoffset_quotient. The right support for asynchronous TSC
> > handling is a bit more complicated unfortunately.
> 
> If your APIC works, your CPUs should get the timer IRQs in alternating order.

Maybe I remeber wrong, but AFIK the io-apic isn't required to scale the
irq load in alternating order, it is perfectly allowed to deliver the
irq always to the same cpu for several seconds. I know the probability
for that to happen is low but it can happen.

Andrea