Re: aio-core why not using SuS? [Re: [rfc] aio-core for 2.5.29 (Re: async-io API registration for 2.5.29)]

Ingo Molnar
2002-08-20T00:30:49Z

On Fri, 16 Aug 2002, Linus Torvalds wrote:

> But if you have such a mapping, then you _cannot_ make a per-task VM
> space, because many tasks will share the same VM. You cannot even do a
> per-cpu mapping change (and rewrite the VM on thread switch), since the
> VM is _shared_ across CPU's, and absolutely has to be in order to work
> with CPU's that do TLB fill in hardware (eg x86).

i'm just trying to insert the notion here that it *is* possible to do
'software TLB fill' on x86 as well - it's just too much pain and very
likely not worth it. The pgd entry of the top 4MB mapping can be filled in
temporarily, the space accessed (causing a hw TLB fill), and then the pgd
entry can be zeroed out again - keeping the 'soft filled TLB' still
intact. This assumes that the intermediate pgd value cannot be observed by
any other CPU - which can be achieved via either cross-CPU calls (lots of
overhead to the TLB miss 'handler'), or the hope that freshly accessed &
rewritten, locked cachelines are not seen by other CPUs, yet. (some CPUs
do define a certain window of non-observation for locked MESI lines, in
which the soft TLB handling stuff can be done, theoretically.) This
necessiates the disabling of interrupts, and worse, NMIs, so it's really
flaky.

once the TLB gets flushed it causes a fault again - at which point the
whole 'sw TLB fill' ordeal has to begin again.

so this is not practical at all, but perhaps interesting. If eg.
kernel-space used 4MB pages only for this purpose then we would not get
many 'TLB misses', because on most (all?) x86 CPUs the large-page TLBs are
isolated from the 4K page TLBs. They could even survive TLB flushes via
the PGE bit set.

but this is so hw-specific that the use of x86 segmentation looks like a
highlevel language in comparison :-)

Ingo