From: David Bronaugh <dbronaugh@linuxboxen.org>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Patch to enable K6-2 and K6-3 processor optimizations
Date: Fri, 9 Aug 2002 10:28:32 -0700 [thread overview]
Message-ID: <20020809102832.05f346a2.dbronaugh@linuxboxen.org> (raw)
In-Reply-To: <1028889079.30103.184.camel@irongate.swansea.linux.org.uk>
On 09 Aug 2002 11:31:19 +0100
Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:
> We can't actually use MMX/FPU instructions in the kernel in the general
> case. That would require saving and restoring the user process floating
> point state - which is extremely expensive
Yes, but that's not all that was implemented here.
>From the GCC 3.1 changelog:
# Prefetch support has been added to the Pentium III, Pentium 4, K6-2, K6-3, and Athlon series.
That's (as I understand it) independent from the floating point instructions.
Also, as a general point (IMO), targeting as specifically as possible (ie, K6-2 or K6-III rather than just K6) will most probably produce the best code for the processor. This also allows for later generations of compilers to make other optimizations and the kernel to take advantage of them.
David Bronaugh
next prev parent reply other threads:[~2002-08-09 17:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-08-09 8:48 Patch to enable K6-2 and K6-3 processor optimizations David Bronaugh
2002-08-09 10:31 ` Alan Cox
2002-08-09 17:28 ` David Bronaugh [this message]
2002-08-09 16:45 ` Josh McKinney
-- strict thread matches above, loose matches on Subject: below --
2002-08-09 8:52 David Bronaugh
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