Re: 2.4.20pre7, aic7xxx-6.2.8: Panic: HOST_MSG_LOOP with invalid SCB 0

Benjamin Herrenschmidt
2002-09-24T07:34:19Z

>No, it is not write posting. It is usually a problem with write
>combining/merging and or read prefetch on devices that do not
>support this feature. The memory BAR on the aic7xxx chips does
>not have the PREFETCH bit set so these types of operations are
>forbidden by the spec. The end result are missed writes and
>state read data leading to all kinds of driver confusion.
>
>Often these issues are really register layout dependent. If
>you never have to access two registers that are right next to
>each other, the chipset can't write combine, etc.

Ok, well. Indeed, adding a read on all writes may help here.
Does this affect the performances significantly ?

Ben.