Re: 2.4.20pre7, aic7xxx-6.2.8: Panic: HOST_MSG_LOOP with invalid SCB 0

Justin T. Gibbs
2002-09-23T21:41:51Z

>> Thanks for explaining me the issue clearly. :)
>
> Hi Justin ! What is the actual breakage here ? Is this just PCI write
> posting ? (that is PCI writes staying in bridge write buffer for
> some time until you flush the whole path with a read). In this
> case those intel & VIA chipsets aren't at fault as this is perfectly
> legal per PCI spec and we'll have problem with all other sort of
> machines, especially machines with stacked PCI<->PCI bridges like
> it's the case for most pmacs.

No, it is not write posting. It is usually a problem with write
combining/merging and or read prefetch on devices that do not
support this feature. The memory BAR on the aic7xxx chips does
not have the PREFETCH bit set so these types of operations are
forbidden by the spec. The end result are missed writes and
state read data leading to all kinds of driver confusion.

Often these issues are really register layout dependent. If
you never have to access two registers that are right next to
each other, the chipset can't write combine, etc.

--
Justin