Re: CPU/cache detection wrong

[Dave Jones <davej@codemonkey.org.uk>]

On Tue, Oct 01, 2002 at 06:03:03PM +0200, Maciej W. Rozycki wrote:

 > > >  Strange -- why not to default to 256K and override it with the value
 > > > obtained from a cache descriptor if != 0, then?
 > > Because the cache descriptor IS zero. So we default to 256K.
 >  You wrote "some of", so I suppose others are OK.

Yes, one stepping only afaik. Though the test in the kernel checks
for 6.11,x with l2==0 just to be sure.
 
 > I meant those others. 
 > Anyway -- is it a new problem?  I can't see it documented in the current
 > P3 spec update.  That's weird -- Intel might hesitate documenting
 > weirdnesses of their chips, however they tend to include such simple and
 > obvious errata in the update.
 > 
 >  The spec actually states the L2 descriptor for the P3 may be as follows:
 > 
 > - 0x43 -- 512kB, unified,
 > - 0x82 -- 256kB, 8-way set associative,
 > - 0x83 -- 512kB, 8-way set associative.
 > 
 > The last descriptor is omitted from the list of known types in cache_table
 > in 2.4.20-pre8 -- could it be the culprit? 

 Added in last nights patch. IIRC, the errata meant there was no
 descriptor at all iirc.
 TBH, I can't recall which document I read about this in, as it was a few
 months back now. I'll look through old mails when I get chance and see if
 I can get to the bottom of it.
 It's possible that this was reported to me, and it is the case you
 describe (missing descriptor), but the old code should have picked
 apart the descriptors in a different way to the new table-lookup,
 so that *should* have worked ok if the descriptor was correct.

		Dave

-- 
| Dave Jones.        http://www.codemonkey.org.uk