Re: [Bug 350] New: i386 context switch very slow compared to 2.4 due to wrmsr (performance)

Steven Cole
2003-03-18T20:17:44Z

On Tue, 2003-03-18 at 12:21, Linus Torvalds wrote:
>
> On Tue, 18 Mar 2003, Brian Gerst wrote:
> >
> > Here's a few more data points:
>
> Ok, this shows the behaviour I was trying to explain:
>
> > vendor_id : AuthenticAMD
> > cpu family : 5
> > model : 8
> > model name : AMD-K6(tm) 3D processor
> > stepping : 12
> > cpu MHz : 451.037
> > empty overhead=105 cycles
> > load overhead=-2 cycles
> > I$ load overhead=30 cycles
> > I$ load overhead=90 cycles
> > I$ store overhead=95 cycles
>
> ie loading from the same cacheline shows bad behaviour, most likely due to
> cache line exclusion. Does anybody have an original Pentium to see if I
> remember that one right?

Does this help?

[steven@trendb steven]$ cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 5
model : 2
model name : Pentium 75 - 200
stepping : 12
cpu MHz : 166.196198
fdiv_bug : no
hlt_bug : no
sep_bug : no
f00f_bug : yes
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr mce cx8
bogomips : 331.78

[steven@trendb steven]$ uptime
12:17pm up 272 days, 6:35, 2 users, load average: 0.02, 0.01, 0.00

[steven@trendb steven]$ ./linus1
empty overhead=76 cycles
load overhead=10 cycles
I$ load overhead=34 cycles
I$ load overhead=23 cycles
I$ store overhead=25 cycles