Re: [Bug 350] New: i386 context switch very slow compared to 2.4 due to wrmsr (performance)

[Thomas Schlichter <schlicht@uni-mannheim.de>]

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Am Dienstag, 18. März 2003 20:21 schrieb Linus Torvalds:
> On Tue, 18 Mar 2003, Brian Gerst wrote:
> > Here's a few more data points:
>
> Ok, this shows the behaviour I was trying to explain:
> > vendor_id       : AuthenticAMD
> > cpu family      : 5
> > model           : 8
> > model name      : AMD-K6(tm) 3D processor
> > stepping        : 12
> > cpu MHz         : 451.037
> > empty overhead=105 cycles
> > load overhead=-2 cycles
> > I$ load overhead=30 cycles
> > I$ load overhead=90 cycles
> > I$ store overhead=95 cycles
>
> ie loading from the same cacheline shows bad behaviour, most likely due to
> cache line exclusion. Does anybody have an original Pentium to see if I
> remember that one right?

Yes, you are right!
For an old Pentium-I with 133MHz (running FreeBSD, so I cannot provide 
cpuinfo-data :-( ) I get following:

empty overhead=73 cycles
load overhead=0 cycles
I$ load overhead=88 cycles
I$ load overhead=96 cycles
I$ store overhead=72 cycles

And just to provide data for the AMD K6-III :

vendor_id       : AuthenticAMD
cpu family      : 5
model           : 9
model name      : AMD-K6(tm) 3D+ Processor
stepping        : 1
cpu MHz         : 450.791
cache size      : 256 KB

empty overhead=142 cycles
load overhead=89 cycles
I$ load overhead=95 cycles
I$ load overhead=99 cycles
I$ store overhead=91 cycles

       Thomas

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