L2 cache detection in Celeron 2GHz (P4 based)

L2 cache detection in Celeron 2GHz (P4 based)

[Juha Poutiainen]

Hi all

Kernel doesn't seem to detect L2 cache in 2GHz Pentium4 based Celeron. 
Most likely it is working normally (BIOS detects it and no system speed 
is ok), but it's not shown in dmesg or /proc/cpuinfo.

x86info shows that there is something with descriptor 0x3b, and 0x3c 
seems to be 256K L2 cache. So I guess it is as simple as adding a line:

          { 0x3B, LVL_2,      128 },

in arch/i386/kernel/setup.c  after line 2204 (2.4.20) and
in arch/i386/kernel/cpu/intel.c  after line 102 (2.5.65)

I've tried both, they seems to report it fine, but I can't be sure if 
that really is correct id of that cache. Celeron at issue has 128K L2 
cache.

--
pode

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Paul Rolland]

Hello,

> Kernel doesn't seem to detect L2 cache in 2GHz Pentium4 based 
> Celeron. 
> Most likely it is working normally (BIOS detects it and no 
> system speed 
> is ok), but it's not shown in dmesg or /proc/cpuinfo.

Got the same problem...
You can also add that the L1 detection doesn't seem to be correct
either : 
0K Instruction cache, and 8K data cache for L1... This is not much
for instruction, it seems it should be 12K...

Regards,
Paul

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Dave Jones]

On Wed, Mar 19, 2003 at 09:18:04AM +0100, Paul Rolland wrote:

 > You can also add that the L1 detection doesn't seem to be correct
 > either : 
 > 0K Instruction cache, and 8K data cache for L1... This is not much
 > for instruction, it seems it should be 12K...

That should be fixed in recent 2.4s (and not-so-recent 2.5s).
What version are you seeing this problem on?

		Dave

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Paul Rolland]

Hello,

>  > You can also add that the L1 detection doesn't seem to be correct
>  > either : 
>  > 0K Instruction cache, and 8K data cache for L1... This is not much
>  > for instruction, it seems it should be 12K...
> 
> That should be fixed in recent 2.4s (and not-so-recent 2.5s).
> What version are you seeing this problem on?

Quite a recent one : 2.4.20.

Here are the traces :

bash-2.05$ dmesg | grep -i L1 
CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L1 I cache: 0K, L1 D cache: 8K
bash-2.05$ uname -a
Linux addx-01.PAR 2.4.20-watchdog #4 SMP Mon Mar 17 10:57:00 GMT 2003
i686 unknown

bash-2.05$ cat /proc/cpuinfo 
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 15
model           : 2
model name      : Intel(R) Celeron(R) CPU 2.00GHz
stepping        : 7
cpu MHz         : 2000.356
cache size      : 8 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips        : 3984.58

Regards,
Paul

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Dave Jones]

On Wed, Mar 19, 2003 at 05:53:13PM +0100, Paul Rolland wrote:

 > >  > You can also add that the L1 detection doesn't seem to be correct
 > >  > either : 
 > >  > 0K Instruction cache, and 8K data cache for L1... This is not much
 > >  > for instruction, it seems it should be 12K...
 > > 
 > > That should be fixed in recent 2.4s (and not-so-recent 2.5s).
 > > What version are you seeing this problem on?
 > 
 > Quite a recent one : 2.4.20.

Fixed as of 2.4.21pre1. The fix went in on 2nd December, and pre1 was
tagged as of the 10th December.
 
		Dave

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Dave Jones]

On Wed, Mar 19, 2003 at 08:47:43AM +0200, Juha Poutiainen wrote:

 > x86info shows that there is something with descriptor 0x3b, and 0x3c 
 > seems to be 256K L2 cache. So I guess it is as simple as adding a line:
 > 
 >           { 0x3B, LVL_2,      128 },
 > 
 > in arch/i386/kernel/setup.c  after line 2204 (2.4.20) and
 > in arch/i386/kernel/cpu/intel.c  after line 102 (2.5.65)

Yep, that's exactly the right fix.
x86info cvs updated, and 2.5 patch queued for Linus.
I'll do a 2.4 patch later if you haven't already done so.

 > I've tried both, they seems to report it fine, but I can't be sure if 
 > that really is correct id of that cache. Celeron at issue has 128K L2 
 > cache.

Intel document 24161822.pdf confirms it.

		Dave

Re: L2 cache detection in Celeron 2GHz (P4 based)

[Juha Poutiainen]

> I'll do a 2.4 patch later if you haven't already done so.
> 
Please do, I'm not familiar with doing patches.

> Intel document 24161822.pdf confirms it.
> 
Nice, I was hoping to find some more offician confirmation.

--
pode