* [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
@ 2003-04-01 8:05 Zwane Mwaikambo
2003-04-01 8:22 ` Zwane Mwaikambo
0 siblings, 1 reply; 9+ messages in thread
From: Zwane Mwaikambo @ 2003-04-01 8:05 UTC (permalink / raw)
To: Linux Kernel; +Cc: Andi Kleen, Dave Jones
Stress tested on 8way PIII 700, Dave, does the C3 have sfence?
Index: linux-2.5.66/arch/i386/Kconfig
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/arch/i386/Kconfig,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 Kconfig
--- linux-2.5.66/arch/i386/Kconfig 24 Mar 2003 23:40:26 -0000 1.1.1.1
+++ linux-2.5.66/arch/i386/Kconfig 1 Apr 2003 08:04:42 -0000
@@ -368,6 +368,11 @@ config X86_PREFETCH
depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
default y
+config X86_SSE
+ bool
+ depends on MK7 || MPENTIUMIII || MVIAC3_2
+ default y
+
config X86_SSE2
bool
depends on MK8 || MPENTIUM4
Index: linux-2.5.66/include/asm-i386/system.h
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/include/asm-i386/system.h,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 system.h
--- linux-2.5.66/include/asm-i386/system.h 24 Mar 2003 23:40:20 -0000 1.1.1.1
+++ linux-2.5.66/include/asm-i386/system.h 1 Apr 2003 05:39:00 -0000
@@ -355,11 +355,15 @@ static inline unsigned long __cmpxchg(vo
#define read_barrier_depends() do { } while(0)
+#ifdef CONFIG_X86_SSE
+#define wmb() __asm__ __volatile__ ("sfence;": : :"memory")
+#else
#ifdef CONFIG_X86_OOSTORE
#define wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
#else
#define wmb() __asm__ __volatile__ ("": : :"memory")
#endif
+#endif /* CONFIG_X86_SSE */
#ifdef CONFIG_SMP
#define smp_mb() mb()
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 8:05 [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?) Zwane Mwaikambo
@ 2003-04-01 8:22 ` Zwane Mwaikambo
2003-04-01 10:11 ` Andi Kleen
0 siblings, 1 reply; 9+ messages in thread
From: Zwane Mwaikambo @ 2003-04-01 8:22 UTC (permalink / raw)
To: Linux Kernel; +Cc: Andi Kleen, Dave Jones
On Tue, 1 Apr 2003, Zwane Mwaikambo wrote:
> +config X86_SSE
> + bool
> + depends on MK7 || MPENTIUMIII || MVIAC3_2
> + default y
> +
Bad option to flag against as pointed out by someone, seeing as K7
implimented half the SSE instructions.
urgh...
--
function.linuxpower.ca
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 8:22 ` Zwane Mwaikambo
@ 2003-04-01 10:11 ` Andi Kleen
2003-04-01 11:28 ` Dave Jones
0 siblings, 1 reply; 9+ messages in thread
From: Andi Kleen @ 2003-04-01 10:11 UTC (permalink / raw)
To: Zwane Mwaikambo; +Cc: Linux Kernel, Dave Jones
On Tue, 2003-04-01 at 10:22, Zwane Mwaikambo wrote:
> On Tue, 1 Apr 2003, Zwane Mwaikambo wrote:
>
> > +config X86_SSE
> > + bool
> > + depends on MK7 || MPENTIUMIII || MVIAC3_2
> > + default y
> > +
>
> Bad option to flag against as pointed out by someone, seeing as K7
> implimented half the SSE instructions.
SSE2 != SSE1. K7 has SSE1, like the Pentium 3.
X86_SSE is SSE1
sfence is part of SSE2. That's X86_SSE2
-Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 10:11 ` Andi Kleen
@ 2003-04-01 11:28 ` Dave Jones
2003-04-01 11:49 ` Andi Kleen
0 siblings, 1 reply; 9+ messages in thread
From: Dave Jones @ 2003-04-01 11:28 UTC (permalink / raw)
To: Andi Kleen; +Cc: Zwane Mwaikambo, Linux Kernel
On Tue, Apr 01, 2003 at 12:11:00PM +0200, Andi Kleen wrote:
> sfence is part of SSE2. That's X86_SSE2
I'm not so sure this is correct. A quick google suggests
otherwise, and the C3 Nehemiah (which only supports SSE1) seems
to run sfence instructions just fine.
Dave
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 11:28 ` Dave Jones
@ 2003-04-01 11:49 ` Andi Kleen
2003-04-01 16:07 ` Zwane Mwaikambo
0 siblings, 1 reply; 9+ messages in thread
From: Andi Kleen @ 2003-04-01 11:49 UTC (permalink / raw)
To: Dave Jones; +Cc: Zwane Mwaikambo, Linux Kernel
On Tue, 2003-04-01 at 13:28, Dave Jones wrote:
> On Tue, Apr 01, 2003 at 12:11:00PM +0200, Andi Kleen wrote:
> > sfence is part of SSE2. That's X86_SSE2
>
> I'm not so sure this is correct. A quick google suggests
> otherwise, and the C3 Nehemiah (which only supports SSE1) seems
> to run sfence instructions just fine.
Yes, you're correct. It was SSE1, not SSE2.
The problem Zwane encountered is that early Athlons don't support SSE1,
only XP+ do
To use it he would need an a new CONFIG split for Athlon XP and earlier
Athlon. iirc it didn't make much difference on the athlon anyways which
has quite fast locked operations on exclusive cachelines - sfence seems
to be more useful on P4.
-Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 11:49 ` Andi Kleen
@ 2003-04-01 16:07 ` Zwane Mwaikambo
2003-04-01 16:26 ` Dave Jones
0 siblings, 1 reply; 9+ messages in thread
From: Zwane Mwaikambo @ 2003-04-01 16:07 UTC (permalink / raw)
To: Andi Kleen; +Cc: Dave Jones, Linux Kernel
On Tue, 1 Apr 2003, Andi Kleen wrote:
> Yes, you're correct. It was SSE1, not SSE2.
>
> The problem Zwane encountered is that early Athlons don't support SSE1,
> only XP+ do
hmm wouldn't they illegal op? Some tested this on an Athlon 600.
> To use it he would need an a new CONFIG split for Athlon XP and earlier
> Athlon. iirc it didn't make much difference on the athlon anyways which
> has quite fast locked operations on exclusive cachelines - sfence seems
> to be more useful on P4.
How about this instead then;
Index: linux-2.5.66/arch/i386/Kconfig
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/arch/i386/Kconfig,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 Kconfig
--- linux-2.5.66/arch/i386/Kconfig 24 Mar 2003 23:40:26 -0000 1.1.1.1
+++ linux-2.5.66/arch/i386/Kconfig 1 Apr 2003 16:02:46 -0000
@@ -368,6 +368,11 @@ config X86_PREFETCH
depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
default y
+config X86_USE_SFENCE
+ bool
+ depends on MPENTIUM4
+ default y
+
config X86_SSE2
bool
depends on MK8 || MPENTIUM4
Index: linux-2.5.66/include/asm-i386/system.h
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/include/asm-i386/system.h,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 system.h
--- linux-2.5.66/include/asm-i386/system.h 24 Mar 2003 23:40:20 -0000 1.1.1.1
+++ linux-2.5.66/include/asm-i386/system.h 1 Apr 2003 16:03:50 -0000
@@ -355,11 +355,15 @@ static inline unsigned long __cmpxchg(vo
#define read_barrier_depends() do { } while(0)
+#ifdef CONFIG_X86_USE_SFENCE
+#define wmb() __asm__ __volatile__ ("sfence;": : :"memory")
+#else
#ifdef CONFIG_X86_OOSTORE
#define wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
#else
#define wmb() __asm__ __volatile__ ("": : :"memory")
#endif
+#endif /* CONFIG_USE_SFENCE */
#ifdef CONFIG_SMP
#define smp_mb() mb()
--
function.linuxpower.ca
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 16:07 ` Zwane Mwaikambo
@ 2003-04-01 16:26 ` Dave Jones
2003-04-01 18:31 ` Daniel Egger
0 siblings, 1 reply; 9+ messages in thread
From: Dave Jones @ 2003-04-01 16:26 UTC (permalink / raw)
To: Zwane Mwaikambo; +Cc: Andi Kleen, Linux Kernel
On Tue, Apr 01, 2003 at 11:07:21AM -0500, Zwane Mwaikambo wrote:
> > Yes, you're correct. It was SSE1, not SSE2.
> > The problem Zwane encountered is that early Athlons don't support SSE1,
> > only XP+ do
>
> hmm wouldn't they illegal op? Some tested this on an Athlon 600.
I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
opcode compatable with SSE's instruction.
Dave
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 16:26 ` Dave Jones
@ 2003-04-01 18:31 ` Daniel Egger
2003-04-01 23:32 ` Dave Jones
0 siblings, 1 reply; 9+ messages in thread
From: Daniel Egger @ 2003-04-01 18:31 UTC (permalink / raw)
To: Dave Jones; +Cc: Zwane Mwaikambo, Andi Kleen, Linux Kernel Mailinglist
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Am Die, 2003-04-01 um 18.26 schrieb Dave Jones:
> I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
> opcode compatable with SSE's instruction.
At best the enhanced 3dnow had it. I couldn't find it in the regular
3dnow "technology manual" and don't know where I put the darn other
one....
--
Servus,
Daniel
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
2003-04-01 18:31 ` Daniel Egger
@ 2003-04-01 23:32 ` Dave Jones
0 siblings, 0 replies; 9+ messages in thread
From: Dave Jones @ 2003-04-01 23:32 UTC (permalink / raw)
To: Daniel Egger; +Cc: Zwane Mwaikambo, Andi Kleen, Linux Kernel Mailinglist
On Tue, Apr 01, 2003 at 08:31:01PM +0200, Daniel Egger wrote:
> > I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
> > opcode compatable with SSE's instruction.
> At best the enhanced 3dnow had it. I couldn't find it in the regular
> 3dnow "technology manual" and don't know where I put the darn other
> one....
Even the early athlons had 3dnowext, so this is a mystery solved afiacs
Dave
^ permalink raw reply [flat|nested] 9+ messages in thread
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Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2003-04-01 8:05 [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?) Zwane Mwaikambo
2003-04-01 8:22 ` Zwane Mwaikambo
2003-04-01 10:11 ` Andi Kleen
2003-04-01 11:28 ` Dave Jones
2003-04-01 11:49 ` Andi Kleen
2003-04-01 16:07 ` Zwane Mwaikambo
2003-04-01 16:26 ` Dave Jones
2003-04-01 18:31 ` Daniel Egger
2003-04-01 23:32 ` Dave Jones
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