Re: [PATCH] [3/3] PCI segment support

[grundler@dsl2.external.hp.com (Grant Grundler)]

On Tue, Apr 08, 2003 at 06:31:09PM +0100, Matthew Wilcox wrote:
> On Tue, Apr 08, 2003 at 09:21:19PM +0400, Ivan Kokshaysky wrote:
...
> > I believe each PCI controller on these ia64/parisc boxes has its
> > own config space, and can support up to 256 bridged PCI buses, right?

yes - at least "HP Designed" chipsets do.

> > Whether or not these PCI controllers share the same IO or MEM space is
> > irrelevant (because it's entirely implementation specific).
> 
> I think hardware _could_ work like that, but it's never set up to work
> like that in practice.

I interpret "practice" as equivalent to "implementation" in this context.

I hedge by saying "HP designed" because HP tried to sell Intel itanic
boxes until current mckinley boxes became available. And SGI, IBM,
and other vendors are designing their own "high end" ia64 chipsets.
(eg NEC Azusa - 16 CPU itanic).

parisc firmware (both Legacy and PAT PDC) and current IA64 firmware number
the PCI busses.  I didn't want the parisc-linux implementation to
reprogram PCI Bus numbers because:
o lack of PCI Segment support (which I'm glad to see willy is fixing)
o the "view" of devices from both firmware and linux should match.

card-mode dino (PCI controller on GSC HBA) is the only exception where
firmware has no clue about the PCI controller.

hth,
grant