From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S263220AbTDVQAB (ORCPT ); Tue, 22 Apr 2003 12:00:01 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S263225AbTDVQAB (ORCPT ); Tue, 22 Apr 2003 12:00:01 -0400 Received: from deviant.impure.org.uk ([195.82.120.238]:39098 "EHLO deviant.impure.org.uk") by vger.kernel.org with ESMTP id S263220AbTDVQAA (ORCPT ); Tue, 22 Apr 2003 12:00:00 -0400 Date: Tue, 22 Apr 2003 17:11:26 +0100 From: Dave Jones To: Andi Kleen Cc: Arjan van de Ven , Linux Kernel Mailing List Subject: Re: [PATCH] Runtime memory barrier patching Message-ID: <20030422161126.GA13223@suse.de> Mail-Followup-To: Dave Jones , Andi Kleen , Arjan van de Ven , Linux Kernel Mailing List References: <200304220111.h3M1BEp5004047@hera.kernel.org> <1051001038.1419.3.camel@laptop.fenrus.com> <20030422111832.GC2170@averell> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20030422111832.GC2170@averell> User-Agent: Mutt/1.5.4i Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 22, 2003 at 01:18:32PM +0200, Andi Kleen wrote: > You only need Intel and AMD prefetch. For all Athlons the SSE prefetches > work (because we force the SSE MSR bit to on). Except those before Athlon XP which didn't have SSE. Dave