From: Dave Jones <davej@redhat.com>
To: Jamie Lokier <jamie@shareable.org>
Cc: michaelc <michaelc@turbolinux.com.cn>, linux-kernel@vger.kernel.org
Subject: Re: about PENTIUM4 cache line
Date: Sun, 17 Aug 2003 21:42:49 +0100 [thread overview]
Message-ID: <20030817204249.GA2225@redhat.com> (raw)
In-Reply-To: <20030817202534.GC3543@mail.jlokier.co.uk>
On Sun, Aug 17, 2003 at 09:25:35PM +0100, Jamie Lokier wrote:
> michaelc wrote:
> > I read the Intel IA-32 developer's manual recently, and I found
> > the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
> > wide, but the thing make me confused is that the default value
> > CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
> > not 6? Any expanation about this would be appreciated!
>
> I don't recall seeing an answer to this.
> Was there one?
ISTR it was something to do with how the P4 cachelines are laid out.
Something like 2 sectors of 64 byte lines.
Dave
--
Dave Jones http://www.codemonkey.org.uk
next prev parent reply other threads:[~2003-08-17 20:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-09 9:03 about PENTIUM4 cache line michaelc
2001-08-08 11:52 ` shutdown on pressing the ATX power button Sergei Haller
2001-08-09 17:56 ` Pavel Machek
2003-08-17 20:25 ` about PENTIUM4 cache line Jamie Lokier
2003-08-17 20:36 ` David B. Stevens
2003-08-17 20:45 ` Dave Jones
2003-08-17 20:58 ` David B. Stevens
2003-08-17 20:42 ` Dave Jones [this message]
2003-08-17 22:52 ` Philippe Elie
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