Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Russell King <rmk@arm.linux.org.uk>]

On Tue, Sep 02, 2003 at 06:34:15AM +0100, Jamie Lokier wrote:
> Russell King wrote:
> > If you take a moment to think about what should be going on -
> > 
> > - first write gets translated to physical address, and the address with
> >   the data is placed in the write buffer.
> > - second write gets translated to the same physical address, and the
> >   address and data is placed into the write buffer such that we store
> >   the first write then the second write to the same physical memory.
> > - reading from the first mapping should return the second writes value
> >   no matter what.
> 
> That is an incomplete explanation, because it should never be possible
> for reads to access data from the write buffer which isn't the most
> recent.

Umm, that's what I said.

> > ARM doesn't do any of those tricks.
> 
> Don't some of the ARMs executed two instructions concurrently, like
> the original Pentium?

Nope - they're all single issue CPUs, and, if non-buggy, they guarantee
that stores never bypass loads.  (In a later architecture revision, this
is controllable.)

Remember - ARM CPUs aren't a high spec desktop CPU.  They're an embedded
CPU where power consumption matters.  Superscalar/multiple issue/high
performance isn't viable in such many embedded environments.

-- 
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html