Re: [RFC] Relaxed PIO read vs. DMA write ordering

[Grant Grundler <grundler@parisc-linux.org>]

On Thu, Jan 08, 2004 at 11:13:47PM -0800, Jeremy Higdon wrote:
> What if the host/bridge sets the RO bit on a PIO read?  That would
> allow a PIO read response to bypass a DMA write.

*Any* bridge that is on the common path from CPU/Mem to PCI-X
can choose to implement RO anyway it likes. Even though such a
bridge may not use PCI-X, the entire system must honor the semantics
required by PCI/PCI-X one way or another. RO is optional IMHO.

> Now, maybe that
> doesn't make much sense with respect to PCI-X.  I think it's possible,
> though.  Or can the RO bit only be set by a device?

The ordering of transaction on the way to the device is not the obvious
problem here. It's the ordering of transactions originated by the device.
A read return is generated by the device on PCI-X since PCI-X supports
split transactions.

> In any case, if we can do a PIO read to one address space that flushes
> DMA ahead of it or another address space that does not, then you would
> need a separate version of readX, rather than an extra call to sync
> after the read.

That would be optimal yes.
But a functional pci_sync_consistent() implementation would consist
of a MMIO Read using the address space that enforces ordering.

As I pointed out earlier, the spec clearly states it's up to the
device to specify the ordering, not the device driver. The device
driver can only choose to enable the feature or not.

grant