From: "David S. Miller" <davem@redhat.com>
To: grundler@parisc-linux.org
Cc: jgarzik@redhat.com, linux-kernel@vger.kernel.org,
linux-net@vger.kernel.org
Subject: Re: [PATCH] 2.6.1 tg3 DMA engine test failure
Date: Fri, 23 Jan 2004 23:32:41 -0800 (PST) [thread overview]
Message-ID: <20040123.233241.59493446.davem@redhat.com> (raw)
In-Reply-To: <20040124073032.GA7265@colo.lackof.org>
From: Grant Grundler <grundler@parisc-linux.org>
Date: Sat, 24 Jan 2004 00:30:32 -0700
My gut feeling is if linux aligns or pads things nicely for any reason,
then the bye enables don't get used or clobber padding.
If the packet data length is an odd number of bytes, there is nothing
we can do about this, and the newer tigon3 chips are going to use a
cacheline burst for the end of the packet with the trailing byte
enables turned off. I've seen this myself and sparc64 PCI controllers
generate a streaming byte hole error interrupt when it occurs and I
get messages logged in dmesg :)
Maybe keep a shorter note about the bit changed meaning in later models
just to document the issues.
We can "document it" by having the setting of this bit be protected by
chip version numbers. I'd happily accept such a patch.
next prev parent reply other threads:[~2004-01-24 7:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-01-24 1:36 [PATCH] 2.6.1 tg3 DMA engine test failure Grant Grundler
2004-01-24 5:00 ` David S. Miller
2004-01-24 7:30 ` Grant Grundler
2004-01-24 7:32 ` David S. Miller [this message]
2004-01-24 21:15 ` Jeff Garzik
2004-01-24 21:14 ` David S. Miller
2004-01-25 1:48 ` Grant Grundler
2004-01-25 1:53 ` Jeff Garzik
2004-01-25 5:31 ` Grant Grundler
2004-01-25 7:11 ` David S. Miller
2004-01-25 2:13 ` Grant Grundler
2004-01-26 7:52 ` David S. Miller
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