From: Deepak Saxena <dsaxena@plexity.net>
To: "David S. Miller" <davem@redhat.com>
Cc: Matt Porter <mporter@kernel.crashing.org>,
lists@mdiehl.de, linux-kernel@vger.kernel.org
Subject: Re: [Patch] dma_sync_to_device
Date: Wed, 11 Feb 2004 11:57:25 -0700 [thread overview]
Message-ID: <20040211185725.GA25179@plexity.net> (raw)
In-Reply-To: <20040211103056.69e4660e.davem@redhat.com>
On Feb 11 2004, at 10:30, David S. Miller was caught saying:
> On Wed, 11 Feb 2004 11:18:00 -0700
> Matt Porter <mporter@kernel.crashing.org> wrote:
>
> > Sure, other non cache coherent arch's that I'm aware of (PPC, ARM, etc.)
> > already implement the least expensive cache operations based on the
> > direction parameter in pci_dma_sync_single(). On PPC, we do the right
> > thing based on each of three valid directions, I don't yet see what
> > additional information pci_dma_sync_to_device_single() provides.
>
> There are two points in time where you want to sync:
>
> 1) Right after the device has done a DMA transaction, and the cpu
> wishes to read/write the datum.
>
> 2) Right after the cpu has read/write the datum, and we like to let the
> device DMA to/from the thing again.
>
> That is the distinction provided by the two interfaces.
>
> Consider something like MIPS, cache flushes needed for both of the above
> operations:
>
> 1) pci_map_single(), device DMA's from the buffer.
>
> 2) pci_dma_sync_single(). Cpu writes some new command or
> status flag into the buffer.
>
> 3) pci_dma_sync_to_device_single(), now device is asked to DMA from the buffer
> again.
>
> Cache flushes are needed on MIPS for both step #2 and #3, and different kinds of
> flushes in fact.
>
> Do you understand the need for this now?
Not really. Steps 2 and 3 can be done by simply calling pci_dma_sync_single()
with the appropriate direction flag. I don't understand why a
pci_dma_sync_single() is needed after the device does a DMA from the
buffer and before the CPU writes a command. After the CPU writes data to the
buffer, it can do a pci_dma_sync_single(..., DMA_TO_DEVICE), which causes
a cache flush. Isn't this what we're already doing today? Why do we need
to do a cache flush before the CPU writes data into the buffer which is
then immediatelly going to be flushed?
~Deepak
--
Deepak Saxena - dsaxena at plexity dot net - http://www.plexity.net/
next prev parent reply other threads:[~2004-02-11 18:57 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-10 17:31 [Patch] dma_sync_to_device Martin Diehl
2004-02-10 18:42 ` David S. Miller
2004-02-10 18:59 ` Martin Diehl
2004-02-11 6:17 ` Deepak Saxena
2004-02-11 6:51 ` Martin Diehl
2004-02-11 16:39 ` Deepak Saxena
2004-02-11 17:51 ` David S. Miller
2004-02-11 18:18 ` Matt Porter
2004-02-11 18:30 ` David S. Miller
2004-02-11 18:57 ` Deepak Saxena [this message]
2004-02-11 19:08 ` David S. Miller
2004-02-12 3:46 ` Deepak Saxena
2004-02-12 3:58 ` David S. Miller
2004-02-13 1:49 ` Jamie Lokier
2004-02-14 7:24 ` David S. Miller
2004-02-11 19:23 ` Matt Porter
2004-02-11 19:30 ` David S. Miller
2004-02-11 18:43 ` linux-2.6.2 Kernel Problem Elikster
2004-02-14 11:51 ` Adrian Bunk
-- strict thread matches above, loose matches on Subject: below --
2004-02-13 14:27 [Patch] dma_sync_to_device James Bottomley
2004-02-14 8:51 ` Martin Diehl
2004-02-14 22:34 ` James Bottomley
2004-02-14 23:18 ` David S. Miller
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