Re: can TSC tick with different speeds on SMP?

[James Cleverdon <jamesclv@us.ibm.com>]

IIRC, in the IA64 manuals Intel, by carefully not making any guarantees 
to the contrary, reserved the right to have the TSC-equivalent register 
not be synchronized either to the bus clock or the CPU clock.

This doesn't directly apply to IA32, but may give a hint as to their 
future intentions.


On Monday 21 June 2004 12:02 pm, Kirill Korotaev wrote:
> Hello,
>
> I've got some stupid question to SMP gurus and would be very thankful
> for the details. I suddenly faced an SMP system where different P4
> cpus were installed (with different steppings). This resulted in
> different CPU clock speeds and different speeds of time stamp
> counters on these CPUs. I faced the problem during some timings I
> measured in the kernel.
>
> So the question is "is such system compliant with SMP
> specification?". In old kernels there was a code to syncronize TSCs
> and to detect if they were screwed up. Current kernels do not have
> such code. Is it intentional? I suppose there is some code in kernel
> which won't work find on such systems (real-time threads timing
> accounting and so on).
>
> Thanks in advance,
> Kirill
>
> -
>

-- 
James Cleverdon
IBM LTC (xSeries Linux Solutions)
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot comm