[PATCH] dothan speedstep fix

[PATCH] dothan speedstep fix

[Con Kolivas]

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Hi Jeremy

My new dothan cpu comes up as stepping 6. This patch fixes speedstep 
support for my laptop unless it can come up as multiple stepping values? 
Now all I need is for a way to make it report the correct L2 cache.

Signed-off-by: Con Kolivas <kernel@kolivas.org>

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Index: linux-2.6.8.1-ck/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
===================================================================
--- linux-2.6.8.1-ck.orig/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c	2004-08-15 14:08:04.000000000 +1000
+++ linux-2.6.8.1-ck/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c	2004-08-20 16:52:19.292124878 +1000
@@ -57,7 +57,7 @@ static const struct cpu_id cpu_id_dothan
 	.x86_vendor = X86_VENDOR_INTEL,
 	.x86 = 6,
 	.x86_model = 13,
-	.x86_mask = 1,
+	.x86_mask = 6,
 };
 
 struct cpu_model

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Re: [PATCH] dothan speedstep fix

[Alan Cox]

On Gwe, 2004-08-20 at 07:54, Con Kolivas wrote:
> Hi Jeremy
> 
> My new dothan cpu comes up as stepping 6. This patch fixes speedstep 
> support for my laptop unless it can come up as multiple stepping values? 
> Now all I need is for a way to make it report the correct L2 cache.

The patch I posted to l/k a few minutea ago should fix the L2 cache
reporting. 

Re: [PATCH] dothan speedstep fix

[Con Kolivas]

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Alan Cox wrote:
> On Gwe, 2004-08-20 at 07:54, Con Kolivas wrote:
> 
>>Hi Jeremy
>>
>>My new dothan cpu comes up as stepping 6. This patch fixes speedstep 
>>support for my laptop unless it can come up as multiple stepping values? 
>>Now all I need is for a way to make it report the correct L2 cache.
> 
> 
> The patch I posted to l/k a few minutea ago should fix the L2 cache
> reporting. 

Looks like you preempted DaveJ by a handful of emails.

Both patches look good (especially since they're identical ;))

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 13
model name      : Intel(R) Pentium(R) M processor 1.70GHz
stepping        : 6
cpu MHz         : 1700.414
cache size      : 2048 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr mce cx8 apic sep mtrr pge mca 
cmov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe tm2 est
bogomips        : 3366.91


Thanks!

Cheers,
Con

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Re: [PATCH] dothan speedstep fix

[Dave Jones]

On Sat, Aug 21, 2004 at 12:51:19AM +1000, Con Kolivas wrote:
 > Alan Cox wrote:
 > >On Gwe, 2004-08-20 at 07:54, Con Kolivas wrote:
 > >
 > >>Hi Jeremy
 > >>
 > >>My new dothan cpu comes up as stepping 6. This patch fixes speedstep 
 > >>support for my laptop unless it can come up as multiple stepping values? 
 > >>Now all I need is for a way to make it report the correct L2 cache.
 > >
 > >
 > >The patch I posted to l/k a few minutea ago should fix the L2 cache
 > >reporting. 
 > 
 > Looks like you preempted DaveJ by a handful of emails.
 > 
 > Both patches look good (especially since they're identical ;))

Not quite 8-)  Alan's missed off 0x7f

		Dave

Re: [PATCH] dothan speedstep fix

[Dave Jones]

On Fri, Aug 20, 2004 at 04:54:46PM +1000, Con Kolivas wrote:

 > Now all I need is for a way to make it report the correct L2 cache.

How's this look ?

		Dave

Update Intel cache descriptor decoding to match latest
Intel Documentation (24161827.pdf)

Signed-off-by: Dave Jones <davej@redhat.com>

--- FC2/arch/i386/kernel/cpu/intel.c~	2004-08-20 15:15:32.049821280 +0100
+++ FC2/arch/i386/kernel/cpu/intel.c	2004-08-20 15:17:34.407220128 +0100
@@ -96,10 +96,13 @@
 	{ 0x70, LVL_TRACE,  12 },
 	{ 0x71, LVL_TRACE,  16 },
 	{ 0x72, LVL_TRACE,  32 },
+	{ 0x78, LVL_2,		1024 },
 	{ 0x79, LVL_2,      128 },
 	{ 0x7a, LVL_2,      256 },
 	{ 0x7b, LVL_2,      512 },
 	{ 0x7c, LVL_2,      1024 },
+	{ 0x7d, LVL_2,		2048 },
+	{ 0x7f, LVL_2,		512 },
 	{ 0x82, LVL_2,      256 },
 	{ 0x83, LVL_2,      512 },
 	{ 0x84, LVL_2,      1024 },