Re: [PATCH] pci-mmconfig fix for 2.6.9

[Grant Grundler <grundler@parisc-linux.org>]

On Fri, Nov 12, 2004 at 11:23:06AM -0800, Michael Chan wrote:
> Hi Grant,
> 
> I think it is well documented that config cycles are non-posted in PCI,
> PCIX, and PCI Express specs as you pointed out. The only ambiguity is
> whether the mmconfig memory cycle from the CPU to the chipset is posted
> or not.

sorry - I was wrongly assuming mmconfig has to follow the same
semantics as config since it's intended as a replacement.

In short, the ECN answers Andi's question with "Yes" - thanks for
pointing it out.
For those who don't want to read the whole ECN, bits of it below.

>  The Implementation Note in the MMCONFIG ECN from pcisig (link
> below) allows the mmconfig write cycle to be posted, meaning mmconfig
> write cycle can complete before the real config write cycle completes.

Yes. I found it on page 5 of PciEx_ECN_MMCONFIG_040217.pdf.
AFAICT, this section only applies to "systems that implement a
processor-architecture-specific firmware interface standard".
e.g. ia64 SAL calls.

> That's why we needed confirmations from chipset engineers.

Well, Intel confirmed existing chipset comply with this bit of the ECN:
| For systems that are PC-compatible, or that do not implement a
| processor-architecture-specific firmware interface standard that
| allows access to the Configuration Space, the enhanced configuration
| access mechanism is required as defined in this section.
....
| The system hardware must provide a method for the system software
| to guarantee that a write transaction using the enhanced configuration
| access mechanism is completed by the completer before system software
| execution continues.


> http://www.pcisig.com/specifications/pciexpress/specifications/specifica
> tions

I assumed this one was meant:
http://www.pcisig.com/specifications/pciexpress/PciEx_ECN_MMCONFIG_040217.pdf

thanks,
grant