Re: [PATCH] pci-mmconfig fix for 2.6.9

[Andi Kleen <ak@suse.de>]

On Sat, Nov 13, 2004 at 12:46:34PM -0700, Grant Grundler wrote:
> On Sat, Nov 13, 2004 at 08:22:50AM -0800, Michael Chan wrote:
> > > If I got the discussion so far correctly then the PCI-SGI spec does not
> > > guarantee that there is no posting, but you know that the chipset
> > > you are using right now doesn't do it.
> > 
> > Yes, that's my understanding of the spec. Grant Grundler does not agree
> >  and thinks that non-posting is the only compliant implementation.
> 
> That's not what I said. I think we do agree. I'll rephrase.
> The code currently in arch/i386 and arch/x86_64 support a chipset that
> is compliant with the part of the spec that requires non-postable
> config writes.
> 
> Other chipsets can implement postable config space. To be compliant
> with the ECN, the architecture must define a method to guarantee
> the posted writes have reached the target device. I think the
> ECN we've been talking about assumes that method will be implemented
> in firmware somehow and NOT as a direct access method in the OS.

Hmm, but there is no way for the chipset to tell us that this 
is needed. 

Perhaps we really need to special case this and add posted pci config
writes to handle Michael's power management issue properly. 

That would be definitely the safer approach.

> 
> > I wish he was right as it would be the easiest to deal with.
> > We contacted Intel about the out-of-spec readl when writing to
> > the PMCSR to change power state as they were the original author
> > of the mmconfig code. Their solution was to remove the readl after
> > confirming that mmconfig was non-posted on their chipsets.
> 
> That means someone has to introduce a new method to access
> mmconfig if they implement postable writes.


Problem is that it adds silently a very subtle bug and there
is no way I know of for ACPI to tell the firmware it shouldn't use
posting. The driver should know when the read is forbidden though.

-Andi