Re: 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB/with dual cor e dual way

[Andi Kleen <ak@muc.de>]

On Thu, Jun 02, 2005 at 01:42:00PM -0700, YhLu wrote:
>         cpuid(1, &eax, &ebx, &ecx, &edx);
>         smp_num_siblings = (ebx & 0xff0000) >> 16;
> 
> For amd dual core, smp_num_siblings is set to 1, and it mean has two cores.
> 
>                 seq_printf(m, "siblings\t: %d\n",
>                                 c->x86_num_cores * smp_num_siblings);

Yes; that is done so that the scheduler does not set up
SMT scheduling, which is suboptimal for dual core.

Also some time ago the scheduler domain setup tended to break
with SMT and NUMA combined, but that is probably fixed
now. But it also made it advisable to not set the sibling count.

> 
> for Intel it would be 
> 	c->x86_num_cores  is 2 and smp_num_siblings is 2 too....
> 	so every core will be HT....

If that was true, then a true DC+HT machine would report 4.

I doubt it is, but Suresh can probably clarify.

> Function 0000_0001[EBX]
> EBX[23:16] Logical Processor Count. If CPUID Fn[8000_0001, 0000_0001][EDX:
> HTT, ECX:
> CMPLegacy] = 11b, then this field indicates the number of CPU cores in the
> processor.
> Otherwise, this field is reserved.
> 
> what is intel value about cpuid(1) ebx [23:16], when the CPU is dual core,
> but HT is disabled.
> 1?

-Andi