Re: increased translation cache footprint in v2.6

David S. Miller
2005-06-27T19:54:37Z

From: Dan Malek <dan@embeddededge.com>
Date: Mon, 27 Jun 2005 11:57:51 -0400

> Because of the configurability of the address space among text, data,
> IO, and uncached mapping, we simply can't test an address bit and
> build a new TLB entry.

Maybe not by testing a bit, but instead via a range test.

cmp %reg, PAGE_OFFSET_BEGIN
bl not_kernel
cmp %reg, PAGE_OFFSET_END
bge not_kernel

Calculate 8MB PTE here

not_kernel:

That's 4 instructions, completely trivial.

I think you're making this problem more complex than it really
is. There is no reason at all to hold page tables for the direct
physical memory mappings of lowmem if you have any control whatsoever
over the TLB miss handler.

You'll be saving tons of memory accesses, and that alone should
count for some significant performance savings especially on
embedded setups. What's more, you'll get 8MB mappings as well,
decreasing the TLB miss rate.