Re: Attempted summary of "RT patch acceptance" thread, take 2

["Paul E. McKenney" <paulmck@us.ibm.com>]

On Mon, Jul 11, 2005 at 10:25:28AM -0700, Daniel Walker wrote:
> On Mon, 2005-07-11 at 10:19 -0700, Paul E. McKenney wrote:
> 
> > OK, interesting point, though this would apply only to interrupt latency,
> > not to scheduling latency or to latency for any other system services,
> > right?
> 
> Only for interrupt latency, that I know of. 
> 
> > Do you believe that the 50-us delay measured by Kristian and Karim was
> > due to APM or due to hardware (as Karim suspected)?  If the latter,
> > any guesses as to the cause of the holdup?  50 us is a -really- long
> > time for ~100 instructions on today's hardware, even if each instruction
> > misses the cache!
> 
> There are ~100 interrupt off critical sections. Those sections can be
> variable numbers of instructions. I would imagine that whatever maximum
> latency that Kristian and Karim found is the maximum for their hardware.

Does your ~100-instruction estimate include scheduler_tick() interrupt?
>From another thread, I gather that it runs with hardware interrupts
disabled.

						Thanx, Paul