* [-mm PATCH] set correct bit in reload register of Watchdog Timer for Intel 6300 chipset
@ 2005-08-15 21:02 Naveen Gupta
2005-08-15 22:26 ` David Härdeman
0 siblings, 1 reply; 2+ messages in thread
From: Naveen Gupta @ 2005-08-15 21:02 UTC (permalink / raw)
To: wim, david, akpm; +Cc: linux-kernel, ngupta
This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.
Signed-off-by: Naveen Gupta <ngupta@google.com>
Index: linux-2.6.12/drivers/char/watchdog/i6300esb.c
===================================================================
--- linux-2.6.12.orig/drivers/char/watchdog/i6300esb.c 2005-08-15 11:21:35.000000000 -0700
+++ linux-2.6.12/drivers/char/watchdog/i6300esb.c 2005-08-15 11:28:07.000000000 -0700
@@ -109,7 +109,7 @@
spin_lock(&esb_lock);
/* First, reset timers as suggested by the docs */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* Then disable the WDT */
pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@@ -123,7 +123,7 @@
{
spin_lock(&esb_lock);
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush anything here? */
spin_unlock(&esb_lock);
}
@@ -153,7 +153,7 @@
/* Reload */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush everything out? */
Index: linux-2.6.12/drivers/char/watchdog/i6300esb.h
===================================================================
--- linux-2.6.12.orig/drivers/char/watchdog/i6300esb.h 2005-08-15 11:19:01.000000000 -0700
+++ linux-2.6.12/drivers/char/watchdog/i6300esb.h 2005-08-15 11:26:58.000000000 -0700
@@ -54,6 +54,8 @@
#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
+/* Reload register bits */
+#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
/*
* Some magic constants
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [-mm PATCH] set correct bit in reload register of Watchdog Timer for Intel 6300 chipset
2005-08-15 21:02 [-mm PATCH] set correct bit in reload register of Watchdog Timer for Intel 6300 chipset Naveen Gupta
@ 2005-08-15 22:26 ` David Härdeman
0 siblings, 0 replies; 2+ messages in thread
From: David Härdeman @ 2005-08-15 22:26 UTC (permalink / raw)
To: Naveen Gupta; +Cc: wim, akpm, linux-kernel
On Mon, Aug 15, 2005 at 02:02:19PM -0700, Naveen Gupta wrote:
>
>This patch writes into bit 8 of the reload register to perform the
>correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
>Intel 6300ESB chipset.
>
>Signed-off-by: Naveen Gupta <ngupta@google.com>
Acked-by: David Härdeman <david@2gen.com>
Thanks alot Naveen.
//David
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2005-08-15 22:26 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-08-15 21:02 [-mm PATCH] set correct bit in reload register of Watchdog Timer for Intel 6300 chipset Naveen Gupta
2005-08-15 22:26 ` David Härdeman
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox