From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Andy Isaacson <adi@hexapodia.org>
Cc: moreau francis <francis_moreau2000@yahoo.fr>,
"linux-os (Dick Johnson)" <linux-os@analogic.com>,
linux-kernel@vger.kernel.org
Subject: Re: question on memory barrier
Date: Wed, 24 Aug 2005 12:53:53 -0700 [thread overview]
Message-ID: <200508241253.53586.jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <20050824194836.GA26526@hexapodia.org>
On Wednesday, August 24, 2005 12:48 pm, Andy Isaacson wrote:
> The first register write will be completed before the second register
> write because you use writel, which is defined to have the semantics
> you want. (It uses a platform-specific method to guarantee this,
> possibly "volatile" or "asm("eieio")" or whatever method your platform
> requires.)
writel() ensures ordering? Only from one CPU, another CPU issuing a
write at some later time may have its write arrive first. See
Documentation/io_ordering.txt for some documentation I put together on
this issue.
Jesse
next prev parent reply other threads:[~2005-08-24 19:53 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-08-24 12:43 question on memory barrier moreau francis
2005-08-24 13:04 ` linux-os (Dick Johnson)
2005-08-24 17:31 ` moreau francis
2005-08-24 18:22 ` linux-os (Dick Johnson)
2005-08-24 19:32 ` Oliver Neukum
2005-08-24 19:47 ` linux-os (Dick Johnson)
2005-08-24 19:55 ` Oliver Neukum
2005-08-24 19:48 ` Andy Isaacson
2005-08-24 19:53 ` Jesse Barnes [this message]
2005-08-24 21:45 ` Alan Cox
2005-08-24 21:22 ` Jesse Barnes
2005-08-24 20:03 ` linux-os (Dick Johnson)
2005-08-24 20:21 ` Oliver Neukum
2005-08-25 2:25 ` David Schwartz
2005-08-25 8:49 ` Denis Vlasenko
2005-08-25 9:14 ` moreau francis
2005-08-25 10:07 ` Alan Cox
2005-08-25 14:54 ` Andy Isaacson
2005-08-26 7:21 ` moreau francis
2005-08-26 10:37 ` Maciej W. Rozycki
2005-08-25 10:32 ` Maciej W. Rozycki
2005-08-24 21:57 ` Alan Cox
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