From: Rajesh Shah <rajesh.shah@intel.com>
To: "Nguyen, Tom L" <tom.l.nguyen@intel.com>
Cc: Andrew Morton <akpm@osdl.org>,
greg@kroah.com, "Li, Shaohua" <shaohua.li@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: [RFC/PATCH]reconfigure MSI registers after resume
Date: Fri, 2 Sep 2005 12:58:22 -0700 [thread overview]
Message-ID: <20050902125822.A11794@unix-os.sc.intel.com> (raw)
In-Reply-To: <C7AB9DA4D0B1F344BF2489FA165E502409A45B38@orsmsx404.amr.corp.intel.com>; from tom.l.nguyen@intel.com on Thu, Sep 01, 2005 at 01:59:32PM -0700
On Thu, Sep 01, 2005 at 01:59:32PM -0700, Nguyen, Tom L wrote:
> On Thursday, September 01, 2005 1:10 PM Andrew Morton wrote:
> > Is it not possible to do this in some single centralized place?
> Existing pci_save_state(dev)/pci_restore_state(dev) covers only 64 bytes
> of PCI header. One solution is to extend these APIs to cover up to 256
> bytes. What do you think?
>
No, we can't have these generic functions blindly save/restore
device specific parts of the config space (offset 64+). I know
of several chipset devices which have read-clear or write-clear
bits where reading/writing would have bad side effects. If at
all the pci core does this, it needs to explicitly walk the
capability list and save/restore the well known capability
registers only.
Rajesh
next prev parent reply other threads:[~2005-09-02 19:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-01 20:59 [RFC/PATCH]reconfigure MSI registers after resume Nguyen, Tom L
2005-09-02 5:38 ` Greg KH
2005-09-02 19:58 ` Rajesh Shah [this message]
2005-09-02 22:00 ` Andrew Morton
-- strict thread matches above, loose matches on Subject: below --
2005-09-02 18:51 Nguyen, Tom L
2005-09-01 20:01 Nguyen, Tom L
2005-09-01 20:10 ` Andrew Morton
2005-09-01 15:20 Nguyen, Tom L
2005-09-01 19:31 ` Andrew Morton
2005-09-02 1:03 ` Shaohua Li
2005-08-18 5:35 Shaohua Li
2005-08-31 21:43 ` Greg KH
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