Re: PCI bug in 2.6.13

[Vojtech Pavlik <vojtech@suse.cz>]

On Sat, Sep 10, 2005 at 06:41:01PM -0700, Linus Torvalds wrote:

> It looks like your HPT controller.
> 
> 	 00:0b.0 Mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372/372N (rev 04)
> 	 ...
> 	-30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
> 	+30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
> 
> That's a _really_ bad value. It's "enabled" (low bit set) but at address 
> zero in the bad case. 
> 
> My problem is that I don't see what writes that invalid enable bit. The 
> patch that broke things for you explicitly avoids writing any value at 
> _all_, much less one with the rom enabled bit set (in fact, if the enabled 
> bit had been set, the patch wouldn't have made any difference at all for 
> you).
> 
> The HPT driver does some strange things:
> 
>         /* FIXME: Not portable */
>         if (dev->resource[PCI_ROM_RESOURCE].start)
>                 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
>                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
> 
> but that one too _explicitly_ only does so for non-zero resource start
> values. But something clearly wrote 00000001 to your ROM address..

This is interesting. The 0x00000001 means that it's supposed to be an
unassigned I/O (!) space resource ... which obviously fools the if()
statement.


-- 
Vojtech Pavlik
SuSE Labs, SuSE CR