From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Jeff Garzik <jgarzik@pobox.com>
Cc: "Luck, Tony" <tony.luck@intel.com>,
ak@suse.de, torvalds@osdl.org, Greg Edwards <edwardsg@sgi.com>,
linux-kernel@vger.kernel.org, discuss@x86-64.org
Subject: Re: [2/3] Set compatibility flag for 4GB zone on IA64
Date: Sun, 11 Sep 2005 19:58:02 -0700 [thread overview]
Message-ID: <200509111958.02190.jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <4324D70C.3090109@pobox.com>
On Sunday, September 11, 2005 6:17 pm, Jeff Garzik wrote:
> Luck, Tony wrote:
> >>Luck, Tony wrote:
> >>>ia64 isn't all that homogeneous. SGI systems stuff *all* memory
> >>>into the DMA zone as their I/O devices have no 32-bit limits (just
> >>>as well really as there is no memory below 4G on an Altix!).
> >>
> >>SGI machines support random PCI cards, right? If so, you
> >>cannot presume
> >>I/O devices have no 32-bit limits.
> >
> > No, SGI machines don't support random PCI cards. The lowest
> > possible physical address in an Altix is 192GB. Cards that
> > can only DMA to addresses below 4G aren't going to be very
> > useful, are they?
>
> Do the boxes have IOMMUs?
Yes, but they can only support devices that can do 32 bit or above
addressing due to the fact that their IOMMU page tables are only
referenced if the high bit of a 32 bit address is set, iirc.
Anyway, for those boxes, all memory was put in the DMA zone and the I/O
mapping routines failed if devices that didn't support at least 32 bits
tried to do a DMA map.
Jesse
next prev parent reply other threads:[~2005-09-12 2:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-12 1:05 [2/3] Set compatibility flag for 4GB zone on IA64 Luck, Tony
2005-09-12 1:17 ` Jeff Garzik
2005-09-12 2:58 ` Jesse Barnes [this message]
-- strict thread matches above, loose matches on Subject: below --
2005-09-11 20:44 Luck, Tony
2005-09-11 21:05 ` Andi Kleen
2005-09-11 23:24 ` Jeff Garzik
2005-09-12 2:09 ` Chris Wedgwood
2005-09-11 16:59 Andi Kleen
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