Re: [PATCH 2/5] atomic: introduce atomic_inc_not_zero

[Russell King <rmk+lkml@arm.linux.org.uk>]

On Wed, Sep 14, 2005 at 07:18:31PM +0200, Roman Zippel wrote:
> On Thu, 15 Sep 2005, Nick Piggin wrote:
> > Or here is possible pseudo code for an architecture with ll/sc
> > instructions:
> > 
> >   do {
> >     tmp = load_locked(v);
> >     if (!tmp)
> >       break;
> >     tmp++;
> >   } while (!store_cond(v, tmp));
> > 
> >   return tmp;
> > 
> > As opposed to using the cmpxchg version, which would have more
> > loads and conditional branches, AFAIKS.
> 
> I'd prefer to generalize this construct, than polluting atomic.h with all 
> kinds of esoteric atomic operations.
> So you would get:
> 
> 	do {
> 		old = atomic_load_locked(v);
> 		if (!old)
> 			break;
> 		new = old + 1;
> 	} while (!atomic_store_lock(v, old, new));

How do you propose architectures which don't have locked loads implement
this, where the only atomic instruction is an unconditional atomic swap
between memory and CPU register?

-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 Serial core