Re: 4GB memory and Intel Dual-Core system

Re: 4GB memory and Intel Dual-Core system

[Lukas Hejtmanek]

Hello,

I have system with 2 Pentium 4 Xeon EM64T processors using 4GB of RAM.

Kernel is 2.6.13.4 compiled for x86_64 architecture.

Btw, /proc/cpuinfo reports, that only 36 bits are availalable for physical 
memory. Not 40.

# cat /proc/meminfo 
MemTotal:      4075408 kB
MemFree:         23696 kB

# cat /proc/iomem
[...]
dd100000-dd3fffff : PCI Bus #01
  dd100000-dd100fff : 0000:01:00.1
  dd101000-dd101fff : 0000:01:00.3
  dd200000-dd2fffff : PCI Bus #02
    dd200000-dd201fff : 0000:02:02.0
      dd200000-dd200fff : aic79xx
    dd202000-dd203fff : 0000:02:02.1
      dd202000-dd202fff : aic79xx
    dd220000-dd23ffff : 0000:02:03.0
      dd220000-dd23ffff : e1000
    dd240000-dd25ffff : 0000:02:03.1
      dd240000-dd25ffff : e1000
  dd300000-dd3fffff : PCI Bus #03
    dd300000-dd3fffff : 0000:03:04.0
dd400000-deffffff : PCI Bus #06
  dd400000-dd400fff : 0000:06:01.0
  de000000-deffffff : 0000:06:01.0
e0000000-efffffff : reserved
fec00000-fec0ffff : reserved
fee00000-fee00fff : reserved
ff800000-ffbfffff : reserved
fffffc00-ffffffff : reserved
100000000-12fffffff : System RAM

According to /proc/pci it is E7520/E7525 board. It has a number of PCI devices.

-- 
Lukáš Hejtmánek

Re: 4GB memory and Intel Dual-Core system

[Dave Jones]

On Fri, Oct 28, 2005 at 10:58:33PM +0200, Lukas Hejtmanek wrote:
 > Hello,
 > 
 > I have system with 2 Pentium 4 Xeon EM64T processors using 4GB of RAM.
 > 
 > Kernel is 2.6.13.4 compiled for x86_64 architecture.
 > 
 > Btw, /proc/cpuinfo reports, that only 36 bits are availalable for physical 
 > memory. Not 40.

That should be fixed in 2.6.14

		Dave

Re: 4GB memory and Intel Dual-Core system

[Marcel Holtmann]

Hi Dave,

>  > I have system with 2 Pentium 4 Xeon EM64T processors using 4GB of RAM.
>  > 
>  > Kernel is 2.6.13.4 compiled for x86_64 architecture.
>  > 
>  > Btw, /proc/cpuinfo reports, that only 36 bits are availalable for physical 
>  > memory. Not 40.
> 
> That should be fixed in 2.6.14

is this only true for the Xeon series or should it be 40 bits for every
EM64T capable CPU from Intel? I ask, because mine still shows 36 bits
with the latest vanilla from today.

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 15
model           : 4
model name      :               Intel(R) Pentium(R) D CPU 2.80GHz
stepping        : 4
cpu MHz         : 2800.229
cache size      : 1024 KB
physical id     : 0
siblings        : 2
core id         : 0
cpu cores       : 2
fpu             : yes
fpu_exception   : yes
cpuid level     : 5
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl cid cx16 xtpr
bogomips        : 5609.23
clflush size    : 64
cache_alignment : 128
address sizes   : 36 bits physical, 48 bits virtual
power management:

Regards

Marcel

Re: 4GB memory and Intel Dual-Core system

[Dave Jones]

On Sat, Oct 29, 2005 at 01:15:24PM +0200, Marcel Holtmann wrote:
 > Hi Dave,
 > 
 > >  > I have system with 2 Pentium 4 Xeon EM64T processors using 4GB of RAM.
 > >  > 
 > >  > Kernel is 2.6.13.4 compiled for x86_64 architecture.
 > >  > 
 > >  > Btw, /proc/cpuinfo reports, that only 36 bits are availalable for physical 
 > >  > memory. Not 40.
 > > 
 > > That should be fixed in 2.6.14
 > 
 > is this only true for the Xeon series or should it be 40 bits for every
 > EM64T capable CPU from Intel? I ask, because mine still shows 36 bits
 > with the latest vanilla from today.

Actually, I mixed this up a little. 36 bits is 'the norm' for EM64T 
(for right now at least).  However, there were two models that advertised
40 bits, but only actually have 36 bits.

The following patch Andi forwarded never actually made it into 2.6.14.
Definite 2.6.14.1 material IMO.

		Dave

From: Andi Kleen <ak@suse.de>
To: Linus Torvalds <torvalds@osdl.org>
Subject: [PATCH] x86_64/i386: Compute correct MTRR mask on early Noconas
Date: Thu, 13 Oct 2005 02:28:26 +0200
Cc: discuss@x86-64.org, Shaohua Li <shaohua.li@intel.com>, davej@redhat.com


Force correct address space size for MTRR on some 64bit Intel Xeons

They report 40bit, but only have 36bits of physical address space.
This caused problems with setting up the correct masks for MTRR,
resulting in incorrect MTRRs.

CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86
and EM64T). Detail info can be found at:
http://download.intel.com/design/Xeon/specupdt/30240216.pdf
http://download.intel.com/design/Pentium4/specupdt/30235221.pdf

Signed-off-by: Shaohua Li<shaohua.li@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>

Index: linux/arch/i386/kernel/cpu/mtrr/main.c
===================================================================
--- linux.orig/arch/i386/kernel/cpu/mtrr/main.c
+++ linux/arch/i386/kernel/cpu/mtrr/main.c
@@ -626,6 +626,14 @@ void __init mtrr_bp_init(void)
 		if (cpuid_eax(0x80000000) >= 0x80000008) {
 			u32 phys_addr;
 			phys_addr = cpuid_eax(0x80000008) & 0xff;
+			/* CPUID workaround for Intel 0F33/0F34 CPU */
+			if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+			    boot_cpu_data.x86 == 0xF &&
+			    boot_cpu_data.x86_model == 0x3 &&
+			    (boot_cpu_data.x86_mask == 0x3 ||
+			     boot_cpu_data.x86_mask == 0x4))
+				phys_addr = 36;
+
 			size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
 			size_and_mask = ~size_or_mask & 0xfff00000;
 		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
Index: linux/arch/x86_64/kernel/setup.c
===================================================================
--- linux.orig/arch/x86_64/kernel/setup.c
+++ linux/arch/x86_64/kernel/setup.c
@@ -990,6 +990,11 @@ static void __cpuinit init_intel(struct 
 		unsigned eax = cpuid_eax(0x80000008);
 		c->x86_virt_bits = (eax >> 8) & 0xff;
 		c->x86_phys_bits = eax & 0xff;
+		/* CPUID workaround for Intel 0F34 CPU */
+		if (c->x86_vendor == X86_VENDOR_INTEL &&
+		    c->x86 == 0xF && c->x86_model == 0x3 &&
+		    c->x86_mask == 0x4)
+			c->x86_phys_bits = 36;
 	}
 
 	if (c->x86 == 15)

Re: [stable] Re: 4GB memory and Intel Dual-Core system

[Chris Wright]

* Dave Jones (davej@redhat.com) wrote:
> The following patch Andi forwarded never actually made it into 2.6.14.
> Definite 2.6.14.1 material IMO.

Thanks, queued to -stable.  Also, this one is still not upstream.
-chris

Re: [discuss] Re: [stable] Re: 4GB memory and Intel Dual-Core system

[Andi Kleen]

On Monday 31 October 2005 22:04, Chris Wright wrote:
> * Dave Jones (davej@redhat.com) wrote:
> > The following patch Andi forwarded never actually made it into 2.6.14.
> > Definite 2.6.14.1 material IMO.
>
> Thanks, queued to -stable.  Also, this one is still not upstream.

Will be soon, but in general I would prefer if you didn't merge anything
into STABLE that wasn't upstream yet. Otherwise we risk code drift again.

Thanks,
-Andi

Re: [discuss] Re: [stable] Re: 4GB memory and Intel Dual-Core system

[Chris Wright]

* Andi Kleen (ak@suse.de) wrote:
> On Monday 31 October 2005 22:04, Chris Wright wrote:
> > * Dave Jones (davej@redhat.com) wrote:
> > > The following patch Andi forwarded never actually made it into 2.6.14.
> > > Definite 2.6.14.1 material IMO.
> >
> > Thanks, queued to -stable.  Also, this one is still not upstream.
> 
> Will be soon, but in general I would prefer if you didn't merge anything
> into STABLE that wasn't upstream yet. Otherwise we risk code drift again.

Absolutely.  I just put it in the queue to keep from losing it, and
that's why I mentioned it's not upstream yet.  I'm happy to drop it if
you want to resend once it's merged.

thanks,
-chris