AGP serverworks chipset not being initializated properly?

AGP serverworks chipset not being initializated properly?

[Diego Calleja]

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For a while, I've been having this on my dmesg:

agpgart: Xorg tried to set rate=x12. Setting to AGP3 x8 mode.
agpgart: Putting AGP V2 device at 0000:00:00.1 into 2x mode
agpgart: Putting AGP V2 device at 0000:01:00.0 into 2x mode
[drm] Loading R200 Microcode

This is really weird since my motherboard (CNB20HE chipset)
only supports 2x AGP cards and my xorg.conf file has this: 

Section "Device"
        Identifier      "RADEON9200SE"
        Driver          "radeon"
        Option     "AGPMode" "2"
EndSection


Looking at the code I found out that the code path being run  to get
this printk is:
------------------------------------------------------------------
    /* Check to see if we are operating in 3.0 mode */
    if (agp_bridge->mode & AGPSTAT_MODE_3_0)     
	agp_v3_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat); <----------
    else
	agp_v2_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
------------------------------------------------------------------


so it looks like agp_brige->mode is not being initializated properly, it is
sworks-agp.c:serverworks_configure() who initializates it in my box so
something has to be wrong with one of these 2 lines?:
------------------------------------------------------------------
        agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);

        /* Fill in the mode register */
        pci_read_config_dword(serverworks_private.svrwrks_dev,
                              agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
------------------------------------------------------------------


What is going on, is this a know bug, should I just ignore it (it doesn't
harms anything), file a bugzilla bug? My dmesg says:
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: AGP aperture is 128M @ 0xd0000000
agpgart: Detected ServerWorks CNB20HE chipset: No AGP present.
agpgart: Detected ServerWorks CNB20HE chipset: No AGP present.

Full lspci output is included. 




[-- Attachment #2: lspci --]
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0000:00:00.0 Host bridge: Broadcom CNB20-LE Host Bridge (rev 23)
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Region 0: Memory at d0000000 (32-bit, prefetchable) [disabled] [size=128M]
	Region 1: Memory at cffff000 (32-bit, non-prefetchable) [disabled] [size=4K]

0000:00:00.1 PCI bridge: Broadcom CNB20-LE Host Bridge (rev 01) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 64, Cache Line Size: 0x08 (32 bytes)
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=64
	I/O behind bridge: 0000c000-0000cfff
	Memory behind bridge: fe700000-fe7fffff
	Prefetchable memory behind bridge: de400000-fe4fffff
	BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>

0000:00:00.2 Host bridge: Broadcom CNB20HE Host Bridge (rev 01)
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-

0000:00:00.3 Host bridge: Broadcom CNB20HE Host Bridge (rev 01)
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-

0000:00:06.0 Ethernet controller: Intel Corporation 82557/8/9 [Ethernet Pro 100] (rev 08)
	Subsystem: Intel Corporation EtherExpress PRO/100+ Server Adapter (PILA8470B)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (2000ns min, 14000ns max), Cache Line Size: 0x08 (32 bytes)
	Interrupt: pin A routed to IRQ 17
	Region 0: Memory at feafe000 (32-bit, non-prefetchable) [size=4K]
	Region 1: I/O ports at d800 [size=64]
	Region 2: Memory at fe900000 (32-bit, non-prefetchable) [size=1M]
	Capabilities: <available only to root>

0000:00:0f.0 ISA bridge: Broadcom OSB4 South Bridge (rev 50)
	Subsystem: Broadcom OSB4 South Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0

0000:00:0f.1 IDE interface: Broadcom OSB4 IDE Controller (prog-if 8a [Master SecP PriP])
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64
	Region 4: I/O ports at ffa0 [size=16]

0000:00:0f.2 USB Controller: Broadcom OSB4/CSB5 OHCI USB Controller (rev 04) (prog-if 10 [OHCI])
	Subsystem: Broadcom OSB4/CSB5 OHCI USB Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (20000ns max), Cache Line Size: 0x08 (32 bytes)
	Interrupt: pin A routed to IRQ 10
	Region 0: Memory at feaff000 (32-bit, non-prefetchable) [size=4K]

0000:01:00.0 VGA compatible controller: ATI Technologies Inc RV280 [Radeon 9200 SE] (rev 01) (prog-if 00 [VGA])
	Subsystem: Hightech Information System Ltd.: Unknown device 2002
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (2000ns min), Cache Line Size: 0x08 (32 bytes)
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at e0000000 (32-bit, prefetchable) [size=256M]
	Region 1: I/O ports at c800 [size=256]
	Region 2: Memory at fe7f0000 (32-bit, non-prefetchable) [size=64K]
	Expansion ROM at fe7c0000 [disabled] [size=128K]
	Capabilities: <available only to root>

0000:02:02.0 Multimedia audio controller: Creative Labs SB Audigy LS
	Subsystem: Creative Labs SB0410 SBLive! 24-bit
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (500ns min, 5000ns max)
	Interrupt: pin A routed to IRQ 16
	Region 0: I/O ports at ef80 [size=32]
	Capabilities: <available only to root>

Re: AGP serverworks chipset not being initializated properly?

[Dave Jones]

On Mon, Feb 13, 2006 at 02:27:57AM +0100, Diego Calleja wrote:
 > For a while, I've been having this on my dmesg:
 > 
 > agpgart: Xorg tried to set rate=x12. Setting to AGP3 x8 mode.
 > agpgart: Putting AGP V2 device at 0000:00:00.1 into 2x mode
 > agpgart: Putting AGP V2 device at 0000:01:00.0 into 2x mode
 > [drm] Loading R200 Microcode
 > 
 > This is really weird since my motherboard (CNB20HE chipset)
 > only supports 2x AGP cards and my xorg.conf file has this: 

CNB20HE is unsupported (The failure message should actually
be a little better, I'll go fix that).

Docs on this chipset aren't publically available, so it's
unlikely to happen any time soon.

		Dave