From: Andi Kleen <ak@suse.de>
To: Chris Wright <chrisw@sous-sol.org>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
zach@vmware.com, torvalds@osdl.org
Subject: Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Date: Fri, 28 Apr 2006 08:29:28 +0200 [thread overview]
Message-ID: <200604280829.29164.ak@suse.de> (raw)
In-Reply-To: <20060428062704.GH2909@sorel.sous-sol.org>
On Friday 28 April 2006 08:27, Chris Wright wrote:
> * Andi Kleen (ak@suse.de) wrote:
> > On Friday 28 April 2006 07:23, Chris Wright wrote:
> > > * Andi Kleen (ak@suse.de) wrote:
> > > > > +static inline void pmd_clear(pmd_t *pmd)
> > > > > +{
> > > > > + u32 *tmp = (u32 *)pmd;
> > > > > + *tmp = 0;
> > > > > + smp_wmb();
> > > > > + *(tmp + 1) = 0;
> > > > > +}
> > > >
> > > > I think that's still wrong - it should be wmb() not smp_wmb because this
> > > > problem can happen on a UP kernel already.
> > >
> > > I thought the barrier is to keep compiler from reordering not processor.
> >
> > Yes, but with smp_wmb() it will go away on UP. And even on UP the
> > CPU is free to speculate.
>
> I must be confused. Doesn't that become a barrier() on UP?
No it was me who was confused sorry. Somehow i thought it was defined
away for !SMP
(which would make sense because why would you want a compile barrier
for a barrier that is only needed on SMP?)
-Andi
next prev parent reply other threads:[~2006-04-28 6:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200604272001.k3RK1dmX007637@hera.kernel.org>
2006-04-28 5:18 ` [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case Andi Kleen
2006-04-28 5:23 ` Chris Wright
2006-04-28 6:08 ` Andi Kleen
2006-04-28 6:27 ` Chris Wright
2006-04-28 6:29 ` Andi Kleen [this message]
2006-04-28 7:20 ` Nick Piggin
2006-04-28 14:54 ` Linus Torvalds
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