Re: question regarding cacheline size

[Matthew Wilcox <matthew@wil.cx>]

On Thu, Sep 07, 2006 at 01:07:56PM +0100, Russell King wrote:
> I've often wondered why we don't set the cache line size when we set the
> bus master bit - ISTR when I read the PCI spec (2.1 or 2.2) it implied
> that this should be set for bus master operations.

It's not required ... 3.2.1 of pci 2.3 says:

While Memory Write and Invalidate is the only command that requires
implementation of the Cacheline Size register, it is strongly suggested
the memory read commands use it as well. A bridge that prefetches is
responsible for any latent data not consumed by the master.

(obviously this is talking about requirements placed on the device, not
on the OS, but it'd behoove us to help the device out here).

It's also useful to implement it for slave devices.  PCI 2.3 has the
concept of cacheline wrap transactions -- eg with a cacheline size of
0x10, it can transfer data to 0x108, then 0x10C, 0x100, 0x104, then
0x118, etc

So I think we should redo the PCI subsystem to set cacheline size during
the buswalk rather than waiting for drivers to ask for it to be set.