From: Matthew Wilcox <matthew@wil.cx>
To: Arjan van de Ven <arjan@infradead.org>
Cc: Tejun Heo <htejun@gmail.com>,
linux-pci@atrey.karlin.mff.cuni.cz, Greg KH <greg@kroah.com>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: question regarding cacheline size
Date: Thu, 7 Sep 2006 06:40:26 -0600 [thread overview]
Message-ID: <20060907124026.GN2558@parisc-linux.org> (raw)
In-Reply-To: <1157632405.14882.27.camel@laptopd505.fenrus.org>
On Thu, Sep 07, 2006 at 02:33:25PM +0200, Arjan van de Ven wrote:
>
> >
> > So I think we should redo the PCI subsystem to set cacheline size during
> > the buswalk rather than waiting for drivers to ask for it to be set.
>
> ... while allowing for quirks for devices that go puke when this
> register gets written ;)
>
> (afaik there are a few)
So you want:
unsigned int no_cls:1; /* Device pukes on write to Cacheline Size */
in struct pci_dev?
next prev parent reply other threads:[~2006-09-07 12:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-07 8:31 question regarding cacheline size Tejun Heo
2006-09-07 11:11 ` Matthew Wilcox
2006-09-07 11:20 ` Tejun Heo
2006-09-07 12:07 ` Russell King
2006-09-07 12:23 ` Matthew Wilcox
2006-09-07 12:33 ` Arjan van de Ven
2006-09-07 12:40 ` Matthew Wilcox [this message]
2006-09-07 12:53 ` Tejun Heo
2006-09-07 13:04 ` Matthew Wilcox
2006-09-07 13:19 ` Tejun Heo
2006-09-07 15:21 ` Grant Grundler
2006-09-07 15:47 ` Tejun Heo
2006-09-07 16:00 ` Jeff Garzik
2006-09-07 17:00 ` Matthew Wilcox
2006-09-07 16:04 ` Jeff Garzik
2006-09-22 23:47 ` Grant Grundler
2006-09-07 13:30 ` Jeff Garzik
2006-09-07 13:10 ` Russell King
2006-09-07 13:01 ` Arjan van de Ven
2006-09-07 13:02 ` Russell King
2006-09-07 11:59 ` linux-os (Dick Johnson)
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