Re: question regarding cacheline size

[Matthew Wilcox <matthew@wil.cx>]

On Thu, Sep 07, 2006 at 12:00:39PM -0400, Jeff Garzik wrote:
> Tejun Heo wrote:
> >arch/i386/pci/common.c overrides cacheline size to min 32 regardless of 
> >actual size.  So, we seem to be using larger cacheline size for MWI 
> >already.
> 
> It clamps the minimum size to 32, yes, but on modern machines common.c 
> configures it to a larger size.
> 
> 
> >Jeff pointed out that there actually are devices which limit CLS config. 
> > IMHO, making PCI configure CLS automatically and provide helpers to LLD 
> >to override it if necessary should cut it.
> 
> We still have to add a raft of quirks, if we start automatically 
> configurating CLS...  Also, many PCI devices hardcode it to zero.

That's not a problem.  As long as they silently discard the writes to
the CLS register, we'll cope.  If they decide to flip out, then we have
the no_cls flag.

> If we start configuring CLS automatically, I forsee a period of breakage...

Probably.  But it's something we should have done a long time ago.